SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-mx2/pcm038.c

   1 /*
   2  * Copyright 2007 Robert Schwebel <r.schwebel@pengutronix.de>, Pengutronix
   3  * Copyright (C) 2008 Juergen Beisert (kernel@pengutronix.de)
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License
   7  * as published by the Free Software Foundation; either version 2
   8  * of the License, or (at your option) any later version.
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
  17  * MA 02110-1301, USA.
  18  */
  19
  20 #include <linux/platform_device.h>
  21 #include <linux/mtd/physmap.h>
  22 #include <linux/mtd/plat-ram.h>
  23 #include <asm/mach/arch.h>
  24 #include <asm/mach-types.h>
  25 #include <mach/common.h>
  26 #include <mach/hardware.h>
  27 #include <mach/iomux-mx1-mx2.h>
  28 #include <asm/mach/time.h>
  29 #include <mach/imx-uart.h>
  30 #include <mach/board-pcm038.h>
  31
  32 #include "devices.h"
  33
  34 /*
  35  * Phytec's PCM038 comes with 2MiB battery buffered SRAM,
  36  * 16 bit width
  37  */
  38
  39 static struct platdata_mtd_ram pcm038_sram_data = {
  40         .bankwidth = 2,
  41 };
  42
  43 static struct resource pcm038_sram_resource = {
  44         .start = CS1_BASE_ADDR,
  45         .end   = CS1_BASE_ADDR + 512 * 1024 - 1,
  46         .flags = IORESOURCE_MEM,
  47 };
  48
  49 static struct platform_device pcm038_sram_mtd_device = {
  50         .name = "mtd-ram",
  51         .id = 0,
  52         .dev = {
  53                 .platform_data = &pcm038_sram_data,
  54         },
  55         .num_resources = 1,
  56         .resource = &pcm038_sram_resource,
  57 };
  58
  59 /*
  60  * Phytec's phyCORE-i.MX27 comes with 32MiB flash,
  61  * 16 bit width
  62  */
  63 static struct physmap_flash_data pcm038_flash_data = {
  64         .width = 2,
  65 };
  66
  67 static struct resource pcm038_flash_resource = {
  68         .start = 0xc0000000,
  69         .end   = 0xc1ffffff,
  70         .flags = IORESOURCE_MEM,
  71 };
  72
  73 static struct platform_device pcm038_nor_mtd_device = {
  74         .name = "physmap-flash",
  75         .id = 0,
  76         .dev = {
  77                 .platform_data = &pcm038_flash_data,
  78         },
  79         .num_resources = 1,
  80         .resource = &pcm038_flash_resource,
  81 };
  82
  83 static int mxc_uart0_pins[] = {
  84         PE12_PF_UART1_TXD,
  85         PE13_PF_UART1_RXD,
  86         PE14_PF_UART1_CTS,
  87         PE15_PF_UART1_RTS
  88 };
  89
  90 static int uart_mxc_port0_init(struct platform_device *pdev)
  91 {
  92         return mxc_gpio_setup_multiple_pins(mxc_uart0_pins,
  93                         ARRAY_SIZE(mxc_uart0_pins), "UART0");
  94 }
  95
  96 static int uart_mxc_port0_exit(struct platform_device *pdev)
  97 {
  98         mxc_gpio_release_multiple_pins(mxc_uart0_pins,
  99                         ARRAY_SIZE(mxc_uart0_pins));
 100         return 0;
 101 }
 102
 103 static int mxc_uart1_pins[] = {
 104         PE3_PF_UART2_CTS,
 105         PE4_PF_UART2_RTS,
 106         PE6_PF_UART2_TXD,
 107         PE7_PF_UART2_RXD
 108 };
 109
 110 static int uart_mxc_port1_init(struct platform_device *pdev)
 111 {
 112         return mxc_gpio_setup_multiple_pins(mxc_uart1_pins,
 113                         ARRAY_SIZE(mxc_uart1_pins), "UART1");
 114 }
 115
 116 static int uart_mxc_port1_exit(struct platform_device *pdev)
 117 {
 118         mxc_gpio_release_multiple_pins(mxc_uart1_pins,
 119                         ARRAY_SIZE(mxc_uart1_pins));
 120         return 0;
 121 }
 122
 123 static int mxc_uart2_pins[] = { PE10_PF_UART3_CTS,
 124                                 PE9_PF_UART3_RXD,
 125                                 PE10_PF_UART3_CTS,
 126                                 PE9_PF_UART3_RXD };
 127
 128 static int uart_mxc_port2_init(struct platform_device *pdev)
 129 {
 130         return mxc_gpio_setup_multiple_pins(mxc_uart2_pins,
 131                         ARRAY_SIZE(mxc_uart2_pins), "UART2");
 132 }
 133
 134 static int uart_mxc_port2_exit(struct platform_device *pdev)
 135 {
 136         mxc_gpio_release_multiple_pins(mxc_uart2_pins,
 137                         ARRAY_SIZE(mxc_uart2_pins));
 138         return 0;
 139 }
 140
 141 static struct imxuart_platform_data uart_pdata[] = {
 142         {
 143                 .init = uart_mxc_port0_init,
 144                 .exit = uart_mxc_port0_exit,
 145                 .flags = IMXUART_HAVE_RTSCTS,
 146         }, {
 147                 .init = uart_mxc_port1_init,
 148                 .exit = uart_mxc_port1_exit,
 149                 .flags = IMXUART_HAVE_RTSCTS,
 150         }, {
 151                 .init = uart_mxc_port2_init,
 152                 .exit = uart_mxc_port2_exit,
 153                 .flags = IMXUART_HAVE_RTSCTS,
 154         },
 155 };
 156
 157 static int mxc_fec_pins[] = {
 158         PD0_AIN_FEC_TXD0,
 159         PD1_AIN_FEC_TXD1,
 160         PD2_AIN_FEC_TXD2,
 161         PD3_AIN_FEC_TXD3,
 162         PD4_AOUT_FEC_RX_ER,
 163         PD5_AOUT_FEC_RXD1,
 164         PD6_AOUT_FEC_RXD2,
 165         PD7_AOUT_FEC_RXD3,
 166         PD8_AF_FEC_MDIO,
 167         PD9_AIN_FEC_MDC,
 168         PD10_AOUT_FEC_CRS,
 169         PD11_AOUT_FEC_TX_CLK,
 170         PD12_AOUT_FEC_RXD0,
 171         PD13_AOUT_FEC_RX_DV,
 172         PD14_AOUT_FEC_CLR,
 173         PD15_AOUT_FEC_COL,
 174         PD16_AIN_FEC_TX_ER,
 175         PF23_AIN_FEC_TX_EN
 176 };
 177
 178 static void gpio_fec_active(void)
 179 {
 180         mxc_gpio_setup_multiple_pins(mxc_fec_pins,
 181                         ARRAY_SIZE(mxc_fec_pins), "FEC");
 182 }
 183
 184 static void gpio_fec_inactive(void)
 185 {
 186         mxc_gpio_release_multiple_pins(mxc_fec_pins,
 187                         ARRAY_SIZE(mxc_fec_pins));
 188 }
 189
 190 static struct platform_device *platform_devices[] __initdata = {
 191         &pcm038_nor_mtd_device,
 192         &mxc_w1_master_device,
 193         &pcm038_sram_mtd_device,
 194 };
 195
 196 /* On pcm038 there's a sram attached to CS1, we enable the chipselect here and
 197  * setup other stuffs to access the sram. */
 198 static void __init pcm038_init_sram(void)
 199 {
 200         __raw_writel(0x0000d843, CSCR_U(1));
 201         __raw_writel(0x22252521, CSCR_L(1));
 202         __raw_writel(0x22220a00, CSCR_A(1));
 203 }
 204
 205 static void __init pcm038_init(void)
 206 {
 207         gpio_fec_active();
 208         pcm038_init_sram();
 209
 210         mxc_register_device(&mxc_uart_device0, &uart_pdata[0]);
 211         mxc_register_device(&mxc_uart_device1, &uart_pdata[1]);
 212         mxc_register_device(&mxc_uart_device2, &uart_pdata[2]);
 213         mxc_gpio_mode(PE16_AF_RTCK); /* OWIRE */
 214
 215         platform_add_devices(platform_devices, ARRAY_SIZE(platform_devices));
 216
 217 #ifdef CONFIG_MACH_PCM970_BASEBOARD
 218         pcm970_baseboard_init();
 219 #endif
 220 }
 221
 222 static void __init pcm038_timer_init(void)
 223 {
 224         mxc_clocks_init(26000000);
 225         mxc_timer_init("gpt_clk.0");
 226 }
 227
 228 struct sys_timer pcm038_timer = {
 229         .init = pcm038_timer_init,
 230 };
 231
 232 MACHINE_START(PCM038, "phyCORE-i.MX27")
 233         .phys_io        = AIPI_BASE_ADDR,
 234         .io_pg_offst    = ((AIPI_BASE_ADDR_VIRT) >> 18) & 0xfffc,
 235         .boot_params    = PHYS_OFFSET + 0x100,
 236         .map_io         = mxc_map_io,
 237         .init_irq       = mxc_init_irq,
 238         .init_machine   = pcm038_init,
 239         .timer          = &pcm038_timer,
 240 MACHINE_END