2 * arch/arm/mach-mv78xx0/common.c
4 * Core functions for Marvell MV78xx0 SoCs
6 * This file is licensed under the terms of the GNU General Public
7 * License version 2. This program is licensed "as is" without any
8 * warranty of any kind, whether express or implied.
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/platform_device.h>
14 #include <linux/serial_8250.h>
15 #include <linux/mbus.h>
16 #include <linux/mv643xx_eth.h>
17 #include <linux/mv643xx_i2c.h>
18 #include <linux/ata_platform.h>
19 #include <linux/ethtool.h>
20 #include <asm/mach/map.h>
21 #include <asm/mach/time.h>
22 #include <mach/mv78xx0.h>
23 #include <mach/bridge-regs.h>
24 #include <plat/cache-feroceon-l2.h>
25 #include <plat/ehci-orion.h>
26 #include <plat/orion_nand.h>
27 #include <plat/time.h>
31 /*****************************************************************************
33 ****************************************************************************/
34 int mv78xx0_core_index(void)
39 * Read Extra Features register.
41 __asm__("mrc p15, 1, %0, c15, c1, 0" : "=r" (extra));
43 return !!(extra & 0x00004000);
46 static int get_hclk(void)
51 * HCLK tick rate is configured by DEV_D[7:5] pins.
53 switch ((readl(SAMPLE_AT_RESET_LOW) >> 5) & 7) {
70 panic("unknown HCLK PLL setting: %.8x\n",
71 readl(SAMPLE_AT_RESET_LOW));
77 static void get_pclk_l2clk(int hclk, int core_index, int *pclk, int *l2clk)
82 * Core #0 PCLK/L2CLK is configured by bits [13:8], core #1
83 * PCLK/L2CLK by bits [19:14].
85 if (core_index == 0) {
86 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 8) & 0x3f;
88 cfg = (readl(SAMPLE_AT_RESET_LOW) >> 14) & 0x3f;
92 * Bits [11:8] ([17:14] for core #1) configure the PCLK:HCLK
93 * ratio (1, 1.5, 2, 2.5, 3, 3.5, 4, 4.5, 5, 5.5, 6).
95 *pclk = ((u64)hclk * (2 + (cfg & 0xf))) >> 1;
98 * Bits [13:12] ([19:18] for core #1) configure the PCLK:L2CLK
101 *l2clk = *pclk / (((cfg >> 4) & 3) + 1);
104 static int get_tclk(void)
109 * TCLK tick rate is configured by DEV_A[2:0] strap pins.
111 switch ((readl(SAMPLE_AT_RESET_HIGH) >> 6) & 7) {
119 panic("unknown TCLK PLL setting: %.8x\n",
120 readl(SAMPLE_AT_RESET_HIGH));
127 /*****************************************************************************
128 * I/O Address Mapping
129 ****************************************************************************/
130 static struct map_desc mv78xx0_io_desc[] __initdata = {
132 .virtual = MV78XX0_CORE_REGS_VIRT_BASE,
134 .length = MV78XX0_CORE_REGS_SIZE,
137 .virtual = MV78XX0_PCIE_IO_VIRT_BASE(0),
138 .pfn = __phys_to_pfn(MV78XX0_PCIE_IO_PHYS_BASE(0)),
139 .length = MV78XX0_PCIE_IO_SIZE * 8,
142 .virtual = MV78XX0_REGS_VIRT_BASE,
143 .pfn = __phys_to_pfn(MV78XX0_REGS_PHYS_BASE),
144 .length = MV78XX0_REGS_SIZE,
149 void __init mv78xx0_map_io(void)
154 * Map the right set of per-core registers depending on
155 * which core we are running on.
157 if (mv78xx0_core_index() == 0) {
158 phys = MV78XX0_CORE0_REGS_PHYS_BASE;
160 phys = MV78XX0_CORE1_REGS_PHYS_BASE;
162 mv78xx0_io_desc[0].pfn = __phys_to_pfn(phys);
164 iotable_init(mv78xx0_io_desc, ARRAY_SIZE(mv78xx0_io_desc));
168 /*****************************************************************************
170 ****************************************************************************/
171 static struct orion_ehci_data mv78xx0_ehci_data = {
172 .dram = &mv78xx0_mbus_dram_info,
173 .phy_version = EHCI_PHY_NA,
176 static u64 ehci_dmamask = 0xffffffffUL;
179 /*****************************************************************************
181 ****************************************************************************/
182 static struct resource mv78xx0_ehci0_resources[] = {
184 .start = USB0_PHYS_BASE,
185 .end = USB0_PHYS_BASE + 0x0fff,
186 .flags = IORESOURCE_MEM,
188 .start = IRQ_MV78XX0_USB_0,
189 .end = IRQ_MV78XX0_USB_0,
190 .flags = IORESOURCE_IRQ,
194 static struct platform_device mv78xx0_ehci0 = {
195 .name = "orion-ehci",
198 .dma_mask = &ehci_dmamask,
199 .coherent_dma_mask = 0xffffffff,
200 .platform_data = &mv78xx0_ehci_data,
202 .resource = mv78xx0_ehci0_resources,
203 .num_resources = ARRAY_SIZE(mv78xx0_ehci0_resources),
206 void __init mv78xx0_ehci0_init(void)
208 platform_device_register(&mv78xx0_ehci0);
212 /*****************************************************************************
214 ****************************************************************************/
215 static struct resource mv78xx0_ehci1_resources[] = {
217 .start = USB1_PHYS_BASE,
218 .end = USB1_PHYS_BASE + 0x0fff,
219 .flags = IORESOURCE_MEM,
221 .start = IRQ_MV78XX0_USB_1,
222 .end = IRQ_MV78XX0_USB_1,
223 .flags = IORESOURCE_IRQ,
227 static struct platform_device mv78xx0_ehci1 = {
228 .name = "orion-ehci",
231 .dma_mask = &ehci_dmamask,
232 .coherent_dma_mask = 0xffffffff,
233 .platform_data = &mv78xx0_ehci_data,
235 .resource = mv78xx0_ehci1_resources,
236 .num_resources = ARRAY_SIZE(mv78xx0_ehci1_resources),
239 void __init mv78xx0_ehci1_init(void)
241 platform_device_register(&mv78xx0_ehci1);
245 /*****************************************************************************
247 ****************************************************************************/
248 static struct resource mv78xx0_ehci2_resources[] = {
250 .start = USB2_PHYS_BASE,
251 .end = USB2_PHYS_BASE + 0x0fff,
252 .flags = IORESOURCE_MEM,
254 .start = IRQ_MV78XX0_USB_2,
255 .end = IRQ_MV78XX0_USB_2,
256 .flags = IORESOURCE_IRQ,
260 static struct platform_device mv78xx0_ehci2 = {
261 .name = "orion-ehci",
264 .dma_mask = &ehci_dmamask,
265 .coherent_dma_mask = 0xffffffff,
266 .platform_data = &mv78xx0_ehci_data,
268 .resource = mv78xx0_ehci2_resources,
269 .num_resources = ARRAY_SIZE(mv78xx0_ehci2_resources),
272 void __init mv78xx0_ehci2_init(void)
274 platform_device_register(&mv78xx0_ehci2);
278 /*****************************************************************************
280 ****************************************************************************/
281 struct mv643xx_eth_shared_platform_data mv78xx0_ge00_shared_data = {
283 .dram = &mv78xx0_mbus_dram_info,
286 static struct resource mv78xx0_ge00_shared_resources[] = {
289 .start = GE00_PHYS_BASE + 0x2000,
290 .end = GE00_PHYS_BASE + 0x3fff,
291 .flags = IORESOURCE_MEM,
293 .name = "ge err irq",
294 .start = IRQ_MV78XX0_GE_ERR,
295 .end = IRQ_MV78XX0_GE_ERR,
296 .flags = IORESOURCE_IRQ,
300 static struct platform_device mv78xx0_ge00_shared = {
301 .name = MV643XX_ETH_SHARED_NAME,
304 .platform_data = &mv78xx0_ge00_shared_data,
306 .num_resources = ARRAY_SIZE(mv78xx0_ge00_shared_resources),
307 .resource = mv78xx0_ge00_shared_resources,
310 static struct resource mv78xx0_ge00_resources[] = {
313 .start = IRQ_MV78XX0_GE00_SUM,
314 .end = IRQ_MV78XX0_GE00_SUM,
315 .flags = IORESOURCE_IRQ,
319 static struct platform_device mv78xx0_ge00 = {
320 .name = MV643XX_ETH_NAME,
323 .resource = mv78xx0_ge00_resources,
326 void __init mv78xx0_ge00_init(struct mv643xx_eth_platform_data *eth_data)
328 eth_data->shared = &mv78xx0_ge00_shared;
329 mv78xx0_ge00.dev.platform_data = eth_data;
331 platform_device_register(&mv78xx0_ge00_shared);
332 platform_device_register(&mv78xx0_ge00);
336 /*****************************************************************************
338 ****************************************************************************/
339 struct mv643xx_eth_shared_platform_data mv78xx0_ge01_shared_data = {
341 .dram = &mv78xx0_mbus_dram_info,
342 .shared_smi = &mv78xx0_ge00_shared,
345 static struct resource mv78xx0_ge01_shared_resources[] = {
348 .start = GE01_PHYS_BASE + 0x2000,
349 .end = GE01_PHYS_BASE + 0x3fff,
350 .flags = IORESOURCE_MEM,
354 static struct platform_device mv78xx0_ge01_shared = {
355 .name = MV643XX_ETH_SHARED_NAME,
358 .platform_data = &mv78xx0_ge01_shared_data,
361 .resource = mv78xx0_ge01_shared_resources,
364 static struct resource mv78xx0_ge01_resources[] = {
367 .start = IRQ_MV78XX0_GE01_SUM,
368 .end = IRQ_MV78XX0_GE01_SUM,
369 .flags = IORESOURCE_IRQ,
373 static struct platform_device mv78xx0_ge01 = {
374 .name = MV643XX_ETH_NAME,
377 .resource = mv78xx0_ge01_resources,
380 void __init mv78xx0_ge01_init(struct mv643xx_eth_platform_data *eth_data)
382 eth_data->shared = &mv78xx0_ge01_shared;
383 mv78xx0_ge01.dev.platform_data = eth_data;
385 platform_device_register(&mv78xx0_ge01_shared);
386 platform_device_register(&mv78xx0_ge01);
390 /*****************************************************************************
392 ****************************************************************************/
393 struct mv643xx_eth_shared_platform_data mv78xx0_ge10_shared_data = {
395 .dram = &mv78xx0_mbus_dram_info,
396 .shared_smi = &mv78xx0_ge00_shared,
399 static struct resource mv78xx0_ge10_shared_resources[] = {
402 .start = GE10_PHYS_BASE + 0x2000,
403 .end = GE10_PHYS_BASE + 0x3fff,
404 .flags = IORESOURCE_MEM,
408 static struct platform_device mv78xx0_ge10_shared = {
409 .name = MV643XX_ETH_SHARED_NAME,
412 .platform_data = &mv78xx0_ge10_shared_data,
415 .resource = mv78xx0_ge10_shared_resources,
418 static struct resource mv78xx0_ge10_resources[] = {
421 .start = IRQ_MV78XX0_GE10_SUM,
422 .end = IRQ_MV78XX0_GE10_SUM,
423 .flags = IORESOURCE_IRQ,
427 static struct platform_device mv78xx0_ge10 = {
428 .name = MV643XX_ETH_NAME,
431 .resource = mv78xx0_ge10_resources,
434 void __init mv78xx0_ge10_init(struct mv643xx_eth_platform_data *eth_data)
438 eth_data->shared = &mv78xx0_ge10_shared;
439 mv78xx0_ge10.dev.platform_data = eth_data;
442 * On the Z0, ge10 and ge11 are internally connected back
443 * to back, and not brought out.
445 mv78xx0_pcie_id(&dev, &rev);
446 if (dev == MV78X00_Z0_DEV_ID) {
447 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
448 eth_data->speed = SPEED_1000;
449 eth_data->duplex = DUPLEX_FULL;
452 platform_device_register(&mv78xx0_ge10_shared);
453 platform_device_register(&mv78xx0_ge10);
457 /*****************************************************************************
459 ****************************************************************************/
460 struct mv643xx_eth_shared_platform_data mv78xx0_ge11_shared_data = {
462 .dram = &mv78xx0_mbus_dram_info,
463 .shared_smi = &mv78xx0_ge00_shared,
466 static struct resource mv78xx0_ge11_shared_resources[] = {
469 .start = GE11_PHYS_BASE + 0x2000,
470 .end = GE11_PHYS_BASE + 0x3fff,
471 .flags = IORESOURCE_MEM,
475 static struct platform_device mv78xx0_ge11_shared = {
476 .name = MV643XX_ETH_SHARED_NAME,
479 .platform_data = &mv78xx0_ge11_shared_data,
482 .resource = mv78xx0_ge11_shared_resources,
485 static struct resource mv78xx0_ge11_resources[] = {
488 .start = IRQ_MV78XX0_GE11_SUM,
489 .end = IRQ_MV78XX0_GE11_SUM,
490 .flags = IORESOURCE_IRQ,
494 static struct platform_device mv78xx0_ge11 = {
495 .name = MV643XX_ETH_NAME,
498 .resource = mv78xx0_ge11_resources,
501 void __init mv78xx0_ge11_init(struct mv643xx_eth_platform_data *eth_data)
505 eth_data->shared = &mv78xx0_ge11_shared;
506 mv78xx0_ge11.dev.platform_data = eth_data;
509 * On the Z0, ge10 and ge11 are internally connected back
510 * to back, and not brought out.
512 mv78xx0_pcie_id(&dev, &rev);
513 if (dev == MV78X00_Z0_DEV_ID) {
514 eth_data->phy_addr = MV643XX_ETH_PHY_NONE;
515 eth_data->speed = SPEED_1000;
516 eth_data->duplex = DUPLEX_FULL;
519 platform_device_register(&mv78xx0_ge11_shared);
520 platform_device_register(&mv78xx0_ge11);
523 /*****************************************************************************
525 ****************************************************************************/
527 static struct mv64xxx_i2c_pdata mv78xx0_i2c_0_pdata = {
528 .freq_m = 8, /* assumes 166 MHz TCLK */
530 .timeout = 1000, /* Default timeout of 1 second */
533 static struct resource mv78xx0_i2c_0_resources[] = {
535 .start = I2C_0_PHYS_BASE,
536 .end = I2C_0_PHYS_BASE + 0x1f,
537 .flags = IORESOURCE_MEM,
539 .start = IRQ_MV78XX0_I2C_0,
540 .end = IRQ_MV78XX0_I2C_0,
541 .flags = IORESOURCE_IRQ,
546 static struct platform_device mv78xx0_i2c_0 = {
547 .name = MV64XXX_I2C_CTLR_NAME,
549 .num_resources = ARRAY_SIZE(mv78xx0_i2c_0_resources),
550 .resource = mv78xx0_i2c_0_resources,
552 .platform_data = &mv78xx0_i2c_0_pdata,
556 /*****************************************************************************
558 ****************************************************************************/
560 static struct mv64xxx_i2c_pdata mv78xx0_i2c_1_pdata = {
561 .freq_m = 8, /* assumes 166 MHz TCLK */
563 .timeout = 1000, /* Default timeout of 1 second */
566 static struct resource mv78xx0_i2c_1_resources[] = {
568 .start = I2C_1_PHYS_BASE,
569 .end = I2C_1_PHYS_BASE + 0x1f,
570 .flags = IORESOURCE_MEM,
572 .start = IRQ_MV78XX0_I2C_1,
573 .end = IRQ_MV78XX0_I2C_1,
574 .flags = IORESOURCE_IRQ,
579 static struct platform_device mv78xx0_i2c_1 = {
580 .name = MV64XXX_I2C_CTLR_NAME,
582 .num_resources = ARRAY_SIZE(mv78xx0_i2c_1_resources),
583 .resource = mv78xx0_i2c_1_resources,
585 .platform_data = &mv78xx0_i2c_1_pdata,
589 void __init mv78xx0_i2c_init(void)
591 platform_device_register(&mv78xx0_i2c_0);
592 platform_device_register(&mv78xx0_i2c_1);
595 /*****************************************************************************
597 ****************************************************************************/
598 static struct resource mv78xx0_sata_resources[] = {
601 .start = SATA_PHYS_BASE,
602 .end = SATA_PHYS_BASE + 0x5000 - 1,
603 .flags = IORESOURCE_MEM,
606 .start = IRQ_MV78XX0_SATA,
607 .end = IRQ_MV78XX0_SATA,
608 .flags = IORESOURCE_IRQ,
612 static struct platform_device mv78xx0_sata = {
616 .coherent_dma_mask = 0xffffffff,
618 .num_resources = ARRAY_SIZE(mv78xx0_sata_resources),
619 .resource = mv78xx0_sata_resources,
622 void __init mv78xx0_sata_init(struct mv_sata_platform_data *sata_data)
624 sata_data->dram = &mv78xx0_mbus_dram_info;
625 mv78xx0_sata.dev.platform_data = sata_data;
626 platform_device_register(&mv78xx0_sata);
630 /*****************************************************************************
632 ****************************************************************************/
633 static struct plat_serial8250_port mv78xx0_uart0_data[] = {
635 .mapbase = UART0_PHYS_BASE,
636 .membase = (char *)UART0_VIRT_BASE,
637 .irq = IRQ_MV78XX0_UART_0,
638 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
646 static struct resource mv78xx0_uart0_resources[] = {
648 .start = UART0_PHYS_BASE,
649 .end = UART0_PHYS_BASE + 0xff,
650 .flags = IORESOURCE_MEM,
652 .start = IRQ_MV78XX0_UART_0,
653 .end = IRQ_MV78XX0_UART_0,
654 .flags = IORESOURCE_IRQ,
658 static struct platform_device mv78xx0_uart0 = {
659 .name = "serial8250",
662 .platform_data = mv78xx0_uart0_data,
664 .resource = mv78xx0_uart0_resources,
665 .num_resources = ARRAY_SIZE(mv78xx0_uart0_resources),
668 void __init mv78xx0_uart0_init(void)
670 platform_device_register(&mv78xx0_uart0);
674 /*****************************************************************************
676 ****************************************************************************/
677 static struct plat_serial8250_port mv78xx0_uart1_data[] = {
679 .mapbase = UART1_PHYS_BASE,
680 .membase = (char *)UART1_VIRT_BASE,
681 .irq = IRQ_MV78XX0_UART_1,
682 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
690 static struct resource mv78xx0_uart1_resources[] = {
692 .start = UART1_PHYS_BASE,
693 .end = UART1_PHYS_BASE + 0xff,
694 .flags = IORESOURCE_MEM,
696 .start = IRQ_MV78XX0_UART_1,
697 .end = IRQ_MV78XX0_UART_1,
698 .flags = IORESOURCE_IRQ,
702 static struct platform_device mv78xx0_uart1 = {
703 .name = "serial8250",
706 .platform_data = mv78xx0_uart1_data,
708 .resource = mv78xx0_uart1_resources,
709 .num_resources = ARRAY_SIZE(mv78xx0_uart1_resources),
712 void __init mv78xx0_uart1_init(void)
714 platform_device_register(&mv78xx0_uart1);
718 /*****************************************************************************
720 ****************************************************************************/
721 static struct plat_serial8250_port mv78xx0_uart2_data[] = {
723 .mapbase = UART2_PHYS_BASE,
724 .membase = (char *)UART2_VIRT_BASE,
725 .irq = IRQ_MV78XX0_UART_2,
726 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
734 static struct resource mv78xx0_uart2_resources[] = {
736 .start = UART2_PHYS_BASE,
737 .end = UART2_PHYS_BASE + 0xff,
738 .flags = IORESOURCE_MEM,
740 .start = IRQ_MV78XX0_UART_2,
741 .end = IRQ_MV78XX0_UART_2,
742 .flags = IORESOURCE_IRQ,
746 static struct platform_device mv78xx0_uart2 = {
747 .name = "serial8250",
750 .platform_data = mv78xx0_uart2_data,
752 .resource = mv78xx0_uart2_resources,
753 .num_resources = ARRAY_SIZE(mv78xx0_uart2_resources),
756 void __init mv78xx0_uart2_init(void)
758 platform_device_register(&mv78xx0_uart2);
762 /*****************************************************************************
764 ****************************************************************************/
765 static struct plat_serial8250_port mv78xx0_uart3_data[] = {
767 .mapbase = UART3_PHYS_BASE,
768 .membase = (char *)UART3_VIRT_BASE,
769 .irq = IRQ_MV78XX0_UART_3,
770 .flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF,
778 static struct resource mv78xx0_uart3_resources[] = {
780 .start = UART3_PHYS_BASE,
781 .end = UART3_PHYS_BASE + 0xff,
782 .flags = IORESOURCE_MEM,
784 .start = IRQ_MV78XX0_UART_3,
785 .end = IRQ_MV78XX0_UART_3,
786 .flags = IORESOURCE_IRQ,
790 static struct platform_device mv78xx0_uart3 = {
791 .name = "serial8250",
794 .platform_data = mv78xx0_uart3_data,
796 .resource = mv78xx0_uart3_resources,
797 .num_resources = ARRAY_SIZE(mv78xx0_uart3_resources),
800 void __init mv78xx0_uart3_init(void)
802 platform_device_register(&mv78xx0_uart3);
806 /*****************************************************************************
808 ****************************************************************************/
809 static void mv78xx0_timer_init(void)
811 orion_time_init(IRQ_MV78XX0_TIMER_1, get_tclk());
814 struct sys_timer mv78xx0_timer = {
815 .init = mv78xx0_timer_init,
819 /*****************************************************************************
821 ****************************************************************************/
822 static char * __init mv78xx0_id(void)
826 mv78xx0_pcie_id(&dev, &rev);
828 if (dev == MV78X00_Z0_DEV_ID) {
829 if (rev == MV78X00_REV_Z0)
832 return "MV78X00-Rev-Unsupported";
833 } else if (dev == MV78100_DEV_ID) {
834 if (rev == MV78100_REV_A0)
837 return "MV78100-Rev-Unsupported";
838 } else if (dev == MV78200_DEV_ID) {
839 if (rev == MV78100_REV_A0)
842 return "MV78200-Rev-Unsupported";
844 return "Device-Unknown";
848 static int __init is_l2_writethrough(void)
850 return !!(readl(CPU_CONTROL) & L2_WRITETHROUGH);
853 void __init mv78xx0_init(void)
861 core_index = mv78xx0_core_index();
863 get_pclk_l2clk(hclk, core_index, &pclk, &l2clk);
866 printk(KERN_INFO "%s ", mv78xx0_id());
867 printk("core #%d, ", core_index);
868 printk("PCLK = %dMHz, ", (pclk + 499999) / 1000000);
869 printk("L2 = %dMHz, ", (l2clk + 499999) / 1000000);
870 printk("HCLK = %dMHz, ", (hclk + 499999) / 1000000);
871 printk("TCLK = %dMHz\n", (tclk + 499999) / 1000000);
873 mv78xx0_setup_cpu_mbus();
875 #ifdef CONFIG_CACHE_FEROCEON_L2
876 feroceon_l2_init(is_l2_writethrough());
879 mv78xx0_ge00_shared_data.t_clk = tclk;
880 mv78xx0_ge01_shared_data.t_clk = tclk;
881 mv78xx0_ge10_shared_data.t_clk = tclk;
882 mv78xx0_ge11_shared_data.t_clk = tclk;
883 mv78xx0_uart0_data[0].uartclk = tclk;
884 mv78xx0_uart1_data[0].uartclk = tclk;
885 mv78xx0_uart2_data[0].uartclk = tclk;
886 mv78xx0_uart3_data[0].uartclk = tclk;