2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
6 * Copyright (C) 2007 Herbert Valerio Riedel <hvr@gnu.org>
8 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
9 * role in the ep93xx linux community.
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License, or (at
14 * your option) any later version.
17 #include <linux/kernel.h>
18 #include <linux/init.h>
19 #include <linux/spinlock.h>
20 #include <linux/sched.h>
21 #include <linux/interrupt.h>
22 #include <linux/serial.h>
23 #include <linux/tty.h>
24 #include <linux/bitops.h>
25 #include <linux/serial.h>
26 #include <linux/serial_8250.h>
27 #include <linux/serial_core.h>
28 #include <linux/device.h>
30 #include <linux/time.h>
31 #include <linux/timex.h>
32 #include <linux/delay.h>
33 #include <linux/termios.h>
34 #include <linux/amba/bus.h>
35 #include <linux/amba/serial.h>
37 #include <asm/types.h>
38 #include <asm/setup.h>
39 #include <asm/memory.h>
40 #include <asm/hardware.h>
42 #include <asm/system.h>
43 #include <asm/tlbflush.h>
44 #include <asm/pgtable.h>
47 #include <asm/mach/map.h>
48 #include <asm/mach/time.h>
49 #include <asm/mach/irq.h>
50 #include <asm/arch/gpio.h>
52 #include <asm/hardware/vic.h>
55 /*************************************************************************
56 * Static I/O mappings that are needed for all EP93xx platforms
57 *************************************************************************/
58 static struct map_desc ep93xx_io_desc[] __initdata = {
60 .virtual = EP93XX_AHB_VIRT_BASE,
61 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
62 .length = EP93XX_AHB_SIZE,
65 .virtual = EP93XX_APB_VIRT_BASE,
66 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
67 .length = EP93XX_APB_SIZE,
72 void __init ep93xx_map_io(void)
74 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
78 /*************************************************************************
79 * Timer handling for EP93xx
80 *************************************************************************
81 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
82 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
83 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
84 * is free-running, and can't generate interrupts.
86 * The 508 kHz timers are ideal for use for the timer interrupt, as the
87 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
88 * bit timers (timer 1) since we don't need more than 16 bits of reload
89 * value as long as HZ >= 8.
91 * The higher clock rate of timer 4 makes it a better choice than the
92 * other timers for use in gettimeoffset(), while the fact that it can't
93 * generate interrupts means we don't have to worry about not being able
94 * to use this timer for something else. We also use timer 4 for keeping
95 * track of lost jiffies.
97 static unsigned int last_jiffy_time;
99 #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
101 static int ep93xx_timer_interrupt(int irq, void *dev_id)
103 write_seqlock(&xtime_lock);
105 __raw_writel(1, EP93XX_TIMER1_CLEAR);
107 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
108 >= TIMER4_TICKS_PER_JIFFY) {
109 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
113 write_sequnlock(&xtime_lock);
118 static struct irqaction ep93xx_timer_irq = {
119 .name = "ep93xx timer",
120 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
121 .handler = ep93xx_timer_interrupt,
124 static void __init ep93xx_timer_init(void)
126 /* Enable periodic HZ timer. */
127 __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
128 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
129 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
131 /* Enable lost jiffy timer. */
132 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
134 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
137 static unsigned long ep93xx_gettimeoffset(void)
141 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
143 /* Calculate (1000000 / 983040) * offset. */
144 return offset + (53 * offset / 3072);
147 struct sys_timer ep93xx_timer = {
148 .init = ep93xx_timer_init,
149 .offset = ep93xx_gettimeoffset,
153 /*************************************************************************
154 * GPIO handling for EP93xx
155 *************************************************************************/
156 static unsigned char gpio_int_unmasked[3];
157 static unsigned char gpio_int_enabled[3];
158 static unsigned char gpio_int_type1[3];
159 static unsigned char gpio_int_type2[3];
161 /* Port ordering is: A B F */
162 static const u8 int_type1_register_offset[3] = { 0x90, 0xac, 0x4c };
163 static const u8 int_type2_register_offset[3] = { 0x94, 0xb0, 0x50 };
164 static const u8 eoi_register_offset[3] = { 0x98, 0xb4, 0x54 };
165 static const u8 int_en_register_offset[3] = { 0x9c, 0xb8, 0x5c };
167 static void update_gpio_int_params(unsigned port)
171 __raw_writeb(0, EP93XX_GPIO_REG(int_en_register_offset[port]));
173 __raw_writeb(gpio_int_type2[port],
174 EP93XX_GPIO_REG(int_type2_register_offset[port]));
176 __raw_writeb(gpio_int_type1[port],
177 EP93XX_GPIO_REG(int_type1_register_offset[port]));
179 __raw_writeb(gpio_int_unmasked[port] & gpio_int_enabled[port],
180 EP93XX_GPIO_REG(int_en_register_offset[port]));
183 /* Port ordering is: A B F D E C G H */
184 static const u8 data_register_offset[8] = {
185 0x00, 0x04, 0x30, 0x0c, 0x20, 0x08, 0x38, 0x40,
188 static const u8 data_direction_register_offset[8] = {
189 0x10, 0x14, 0x34, 0x1c, 0x24, 0x18, 0x3c, 0x44,
195 static void ep93xx_gpio_set_direction(unsigned line, int direction)
197 unsigned int data_direction_register;
201 data_direction_register =
202 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
204 local_irq_save(flags);
205 if (direction == GPIO_OUT) {
206 if (line >= 0 && line <= EP93XX_GPIO_LINE_MAX_IRQ) {
208 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
209 update_gpio_int_params(line >> 3);
212 v = __raw_readb(data_direction_register);
213 v |= 1 << (line & 7);
214 __raw_writeb(v, data_direction_register);
215 } else if (direction == GPIO_IN) {
216 v = __raw_readb(data_direction_register);
217 v &= ~(1 << (line & 7));
218 __raw_writeb(v, data_direction_register);
220 local_irq_restore(flags);
223 int gpio_direction_input(unsigned gpio)
225 if (gpio > EP93XX_GPIO_LINE_MAX)
228 ep93xx_gpio_set_direction(gpio, GPIO_IN);
232 EXPORT_SYMBOL(gpio_direction_input);
234 int gpio_direction_output(unsigned gpio, int value)
236 if (gpio > EP93XX_GPIO_LINE_MAX)
239 gpio_set_value(gpio, value);
240 ep93xx_gpio_set_direction(gpio, GPIO_OUT);
244 EXPORT_SYMBOL(gpio_direction_output);
246 int gpio_get_value(unsigned gpio)
248 unsigned int data_register;
250 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
252 return !!(__raw_readb(data_register) & (1 << (gpio & 7)));
254 EXPORT_SYMBOL(gpio_get_value);
256 void gpio_set_value(unsigned gpio, int value)
258 unsigned int data_register;
262 data_register = EP93XX_GPIO_REG(data_register_offset[gpio >> 3]);
264 local_irq_save(flags);
265 v = __raw_readb(data_register);
267 v |= 1 << (gpio & 7);
269 v &= ~(1 << (gpio & 7));
270 __raw_writeb(v, data_register);
271 local_irq_restore(flags);
273 EXPORT_SYMBOL(gpio_set_value);
276 /*************************************************************************
277 * EP93xx IRQ handling
278 *************************************************************************/
279 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
281 unsigned char status;
284 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
285 for (i = 0; i < 8; i++) {
286 if (status & (1 << i)) {
287 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_A(0)) + i;
288 desc = irq_desc + gpio_irq;
289 desc_handle_irq(gpio_irq, desc);
293 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
294 for (i = 0; i < 8; i++) {
295 if (status & (1 << i)) {
296 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_B(0)) + i;
297 desc = irq_desc + gpio_irq;
298 desc_handle_irq(gpio_irq, desc);
303 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
306 * map discontiguous hw irq range to continous sw irq range:
308 * IRQ_EP93XX_GPIO{0..7}MUX -> gpio_to_irq(EP93XX_GPIO_LINE_F({0..7})
310 int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
311 int gpio_irq = gpio_to_irq(EP93XX_GPIO_LINE_F(0)) + port_f_idx;
313 desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
316 static void ep93xx_gpio_irq_ack(unsigned int irq)
318 int line = irq_to_gpio(irq);
319 int port = line >> 3;
320 int port_mask = 1 << (line & 7);
322 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE) {
323 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
324 update_gpio_int_params(port);
327 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
330 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
332 int line = irq_to_gpio(irq);
333 int port = line >> 3;
334 int port_mask = 1 << (line & 7);
336 if ((irq_desc[irq].status & IRQ_TYPE_SENSE_MASK) == IRQT_BOTHEDGE)
337 gpio_int_type2[port] ^= port_mask; /* switch edge direction */
339 gpio_int_unmasked[port] &= ~port_mask;
340 update_gpio_int_params(port);
342 __raw_writeb(port_mask, EP93XX_GPIO_REG(eoi_register_offset[port]));
345 static void ep93xx_gpio_irq_mask(unsigned int irq)
347 int line = irq_to_gpio(irq);
348 int port = line >> 3;
350 gpio_int_unmasked[port] &= ~(1 << (line & 7));
351 update_gpio_int_params(port);
354 static void ep93xx_gpio_irq_unmask(unsigned int irq)
356 int line = irq_to_gpio(irq);
357 int port = line >> 3;
359 gpio_int_unmasked[port] |= 1 << (line & 7);
360 update_gpio_int_params(port);
365 * gpio_int_type1 controls whether the interrupt is level (0) or
366 * edge (1) triggered, while gpio_int_type2 controls whether it
367 * triggers on low/falling (0) or high/rising (1).
369 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
371 struct irq_desc *desc = irq_desc + irq;
372 const int gpio = irq_to_gpio(irq);
373 const int port = gpio >> 3;
374 const int port_mask = 1 << (gpio & 7);
376 ep93xx_gpio_set_direction(gpio, GPIO_IN);
380 gpio_int_type1[port] |= port_mask;
381 gpio_int_type2[port] |= port_mask;
382 desc->handle_irq = handle_edge_irq;
385 gpio_int_type1[port] |= port_mask;
386 gpio_int_type2[port] &= ~port_mask;
387 desc->handle_irq = handle_edge_irq;
390 gpio_int_type1[port] &= ~port_mask;
391 gpio_int_type2[port] |= port_mask;
392 desc->handle_irq = handle_level_irq;
395 gpio_int_type1[port] &= ~port_mask;
396 gpio_int_type2[port] &= ~port_mask;
397 desc->handle_irq = handle_level_irq;
400 gpio_int_type1[port] |= port_mask;
401 /* set initial polarity based on current input level */
402 if (gpio_get_value(gpio))
403 gpio_int_type2[port] &= ~port_mask; /* falling */
405 gpio_int_type2[port] |= port_mask; /* rising */
406 desc->handle_irq = handle_edge_irq;
409 pr_err("ep93xx: failed to set irq type %d for gpio %d\n",
414 gpio_int_enabled[port] |= port_mask;
416 desc->status &= ~IRQ_TYPE_SENSE_MASK;
417 desc->status |= type & IRQ_TYPE_SENSE_MASK;
419 update_gpio_int_params(port);
424 static struct irq_chip ep93xx_gpio_irq_chip = {
426 .ack = ep93xx_gpio_irq_ack,
427 .mask_ack = ep93xx_gpio_irq_mask_ack,
428 .mask = ep93xx_gpio_irq_mask,
429 .unmask = ep93xx_gpio_irq_unmask,
430 .set_type = ep93xx_gpio_irq_type,
434 void __init ep93xx_init_irq(void)
438 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
439 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
441 for (gpio_irq = gpio_to_irq(0);
442 gpio_irq <= gpio_to_irq(EP93XX_GPIO_LINE_MAX_IRQ); ++gpio_irq) {
443 set_irq_chip(gpio_irq, &ep93xx_gpio_irq_chip);
444 set_irq_handler(gpio_irq, handle_level_irq);
445 set_irq_flags(gpio_irq, IRQF_VALID);
448 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
449 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
450 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
451 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
452 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
453 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
454 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
455 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
456 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
460 /*************************************************************************
461 * EP93xx peripheral handling
462 *************************************************************************/
463 #define EP93XX_UART_MCR_OFFSET (0x0100)
465 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
466 void __iomem *base, unsigned int mctrl)
471 if (!(mctrl & TIOCM_RTS))
473 if (!(mctrl & TIOCM_DTR))
476 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
479 static struct amba_pl010_data ep93xx_uart_data = {
480 .set_mctrl = ep93xx_uart_set_mctrl,
483 static struct amba_device uart1_device = {
485 .bus_id = "apb:uart1",
486 .platform_data = &ep93xx_uart_data,
489 .start = EP93XX_UART1_PHYS_BASE,
490 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
491 .flags = IORESOURCE_MEM,
493 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
494 .periphid = 0x00041010,
497 static struct amba_device uart2_device = {
499 .bus_id = "apb:uart2",
500 .platform_data = &ep93xx_uart_data,
503 .start = EP93XX_UART2_PHYS_BASE,
504 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
505 .flags = IORESOURCE_MEM,
507 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
508 .periphid = 0x00041010,
511 static struct amba_device uart3_device = {
513 .bus_id = "apb:uart3",
514 .platform_data = &ep93xx_uart_data,
517 .start = EP93XX_UART3_PHYS_BASE,
518 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
519 .flags = IORESOURCE_MEM,
521 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
522 .periphid = 0x00041010,
526 static struct platform_device ep93xx_rtc_device = {
527 .name = "ep93xx-rtc",
533 static struct resource ep93xx_ohci_resources[] = {
535 .start = EP93XX_USB_PHYS_BASE,
536 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
537 .flags = IORESOURCE_MEM,
540 .start = IRQ_EP93XX_USB,
541 .end = IRQ_EP93XX_USB,
542 .flags = IORESOURCE_IRQ,
546 static struct platform_device ep93xx_ohci_device = {
547 .name = "ep93xx-ohci",
550 .dma_mask = (void *)0xffffffff,
551 .coherent_dma_mask = 0xffffffff,
553 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
554 .resource = ep93xx_ohci_resources,
558 void __init ep93xx_init_devices(void)
563 * Disallow access to MaverickCrunch initially.
565 v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
566 v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
567 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
568 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
570 amba_device_register(&uart1_device, &iomem_resource);
571 amba_device_register(&uart2_device, &iomem_resource);
572 amba_device_register(&uart3_device, &iomem_resource);
574 platform_device_register(&ep93xx_rtc_device);
575 platform_device_register(&ep93xx_ohci_device);