2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
8 * role in the ep93xx linux community.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/sched.h>
20 #include <linux/interrupt.h>
21 #include <linux/serial.h>
22 #include <linux/tty.h>
23 #include <linux/bitops.h>
24 #include <linux/serial_8250.h>
25 #include <linux/serial_core.h>
26 #include <linux/device.h>
28 #include <linux/time.h>
29 #include <linux/timex.h>
30 #include <linux/delay.h>
31 #include <linux/termios.h>
32 #include <linux/amba/bus.h>
33 #include <linux/amba/serial.h>
35 #include <asm/types.h>
36 #include <asm/setup.h>
37 #include <asm/memory.h>
38 #include <asm/hardware.h>
40 #include <asm/system.h>
41 #include <asm/tlbflush.h>
42 #include <asm/pgtable.h>
45 #include <asm/mach/map.h>
46 #include <asm/mach/time.h>
47 #include <asm/mach/irq.h>
48 #include <asm/arch/gpio.h>
50 #include <asm/hardware/vic.h>
53 /*************************************************************************
54 * Static I/O mappings that are needed for all EP93xx platforms
55 *************************************************************************/
56 static struct map_desc ep93xx_io_desc[] __initdata = {
58 .virtual = EP93XX_AHB_VIRT_BASE,
59 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
60 .length = EP93XX_AHB_SIZE,
63 .virtual = EP93XX_APB_VIRT_BASE,
64 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
65 .length = EP93XX_APB_SIZE,
70 void __init ep93xx_map_io(void)
72 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
76 /*************************************************************************
77 * Timer handling for EP93xx
78 *************************************************************************
79 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
80 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
81 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
82 * is free-running, and can't generate interrupts.
84 * The 508 kHz timers are ideal for use for the timer interrupt, as the
85 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
86 * bit timers (timer 1) since we don't need more than 16 bits of reload
87 * value as long as HZ >= 8.
89 * The higher clock rate of timer 4 makes it a better choice than the
90 * other timers for use in gettimeoffset(), while the fact that it can't
91 * generate interrupts means we don't have to worry about not being able
92 * to use this timer for something else. We also use timer 4 for keeping
93 * track of lost jiffies.
95 static unsigned int last_jiffy_time;
97 #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
99 static int ep93xx_timer_interrupt(int irq, void *dev_id)
101 write_seqlock(&xtime_lock);
103 __raw_writel(1, EP93XX_TIMER1_CLEAR);
105 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
106 >= TIMER4_TICKS_PER_JIFFY) {
107 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
111 write_sequnlock(&xtime_lock);
116 static struct irqaction ep93xx_timer_irq = {
117 .name = "ep93xx timer",
118 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
119 .handler = ep93xx_timer_interrupt,
122 static void __init ep93xx_timer_init(void)
124 /* Enable periodic HZ timer. */
125 __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
126 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
127 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
129 /* Enable lost jiffy timer. */
130 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
132 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
135 static unsigned long ep93xx_gettimeoffset(void)
139 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
141 /* Calculate (1000000 / 983040) * offset. */
142 return offset + (53 * offset / 3072);
145 struct sys_timer ep93xx_timer = {
146 .init = ep93xx_timer_init,
147 .offset = ep93xx_gettimeoffset,
151 /*************************************************************************
152 * GPIO handling for EP93xx
153 *************************************************************************/
154 static unsigned char gpio_int_unmasked[3];
155 static unsigned char gpio_int_enabled[3];
156 static unsigned char gpio_int_type1[3];
157 static unsigned char gpio_int_type2[3];
159 static void update_gpio_int_params(int abf)
162 __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
163 __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
164 __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
165 __raw_writeb(gpio_int_unmasked[0] & gpio_int_enabled[0], EP93XX_GPIO_A_INT_ENABLE);
166 } else if (abf == 1) {
167 __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
168 __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
169 __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
170 __raw_writeb(gpio_int_unmasked[1] & gpio_int_enabled[1], EP93XX_GPIO_B_INT_ENABLE);
171 } else if (abf == 2) {
172 __raw_writeb(0, EP93XX_GPIO_F_INT_ENABLE);
173 __raw_writeb(gpio_int_type2[2], EP93XX_GPIO_F_INT_TYPE2);
174 __raw_writeb(gpio_int_type1[2], EP93XX_GPIO_F_INT_TYPE1);
175 __raw_writeb(gpio_int_unmasked[2] & gpio_int_enabled[2], EP93XX_GPIO_F_INT_ENABLE);
182 static unsigned char data_register_offset[8] = {
183 0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
186 static unsigned char data_direction_register_offset[8] = {
187 0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
190 void gpio_line_config(int line, int direction)
192 unsigned int data_direction_register;
196 data_direction_register =
197 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
199 local_irq_save(flags);
200 if (direction == GPIO_OUT) {
201 if (line >= 0 && line < 16) {
203 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
204 update_gpio_int_params(line >> 3);
205 } else if (line >= 40 && line < 48) {
207 gpio_int_unmasked[2] &= ~(1 << (line & 7));
208 update_gpio_int_params(2);
211 v = __raw_readb(data_direction_register);
212 v |= 1 << (line & 7);
213 __raw_writeb(v, data_direction_register);
214 } else if (direction == GPIO_IN) {
215 v = __raw_readb(data_direction_register);
216 v &= ~(1 << (line & 7));
217 __raw_writeb(v, data_direction_register);
219 local_irq_restore(flags);
221 EXPORT_SYMBOL(gpio_line_config);
223 int gpio_line_get(int line)
225 unsigned int data_register;
227 data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
229 return !!(__raw_readb(data_register) & (1 << (line & 7)));
231 EXPORT_SYMBOL(gpio_line_get);
233 void gpio_line_set(int line, int value)
235 unsigned int data_register;
239 data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
241 local_irq_save(flags);
242 if (value == EP93XX_GPIO_HIGH) {
243 v = __raw_readb(data_register);
244 v |= 1 << (line & 7);
245 __raw_writeb(v, data_register);
246 } else if (value == EP93XX_GPIO_LOW) {
247 v = __raw_readb(data_register);
248 v &= ~(1 << (line & 7));
249 __raw_writeb(v, data_register);
251 local_irq_restore(flags);
253 EXPORT_SYMBOL(gpio_line_set);
256 /*************************************************************************
257 * EP93xx IRQ handling
258 *************************************************************************/
259 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
261 unsigned char status;
264 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
265 for (i = 0; i < 8; i++) {
266 if (status & (1 << i)) {
267 desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
268 desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc);
272 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
273 for (i = 0; i < 8; i++) {
274 if (status & (1 << i)) {
275 desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
276 desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc);
281 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
283 int gpio_irq = IRQ_EP93XX_GPIO(16) + (((irq + 1) & 7) ^ 4);
285 desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
288 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
290 int line = irq - IRQ_EP93XX_GPIO(0);
291 int port = line >> 3;
293 gpio_int_unmasked[port] &= ~(1 << (line & 7));
294 update_gpio_int_params(port);
297 __raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK);
298 } else if (port == 1) {
299 __raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
300 } else if (port == 2) {
301 __raw_writel(1 << (line & 7), EP93XX_GPIO_F_INT_ACK);
305 static void ep93xx_gpio_irq_mask(unsigned int irq)
307 int line = irq - IRQ_EP93XX_GPIO(0);
308 int port = line >> 3;
310 gpio_int_unmasked[port] &= ~(1 << (line & 7));
311 update_gpio_int_params(port);
314 static void ep93xx_gpio_irq_unmask(unsigned int irq)
316 int line = irq - IRQ_EP93XX_GPIO(0);
317 int port = line >> 3;
319 gpio_int_unmasked[port] |= 1 << (line & 7);
320 update_gpio_int_params(port);
325 * gpio_int_type1 controls whether the interrupt is level (0) or
326 * edge (1) triggered, while gpio_int_type2 controls whether it
327 * triggers on low/falling (0) or high/rising (1).
329 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
334 line = irq - IRQ_EP93XX_GPIO(0);
335 if (line >= 0 && line < 16) {
336 gpio_line_config(line, GPIO_IN);
338 gpio_line_config(EP93XX_GPIO_LINE_F(line-16), GPIO_IN);
344 if (type & IRQT_RISING) {
345 gpio_int_enabled[port] |= 1 << line;
346 gpio_int_type1[port] |= 1 << line;
347 gpio_int_type2[port] |= 1 << line;
348 } else if (type & IRQT_FALLING) {
349 gpio_int_enabled[port] |= 1 << line;
350 gpio_int_type1[port] |= 1 << line;
351 gpio_int_type2[port] &= ~(1 << line);
352 } else if (type & IRQT_HIGH) {
353 gpio_int_enabled[port] |= 1 << line;
354 gpio_int_type1[port] &= ~(1 << line);
355 gpio_int_type2[port] |= 1 << line;
356 } else if (type & IRQT_LOW) {
357 gpio_int_enabled[port] |= 1 << line;
358 gpio_int_type1[port] &= ~(1 << line);
359 gpio_int_type2[port] &= ~(1 << line);
361 gpio_int_enabled[port] &= ~(1 << line);
363 update_gpio_int_params(port);
368 static struct irq_chip ep93xx_gpio_irq_chip = {
370 .ack = ep93xx_gpio_irq_mask_ack,
371 .mask = ep93xx_gpio_irq_mask,
372 .unmask = ep93xx_gpio_irq_unmask,
373 .set_type = ep93xx_gpio_irq_type,
377 void __init ep93xx_init_irq(void)
381 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
382 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
384 for (irq = IRQ_EP93XX_GPIO(0); irq <= IRQ_EP93XX_GPIO(23); irq++) {
385 set_irq_chip(irq, &ep93xx_gpio_irq_chip);
386 set_irq_handler(irq, handle_level_irq);
387 set_irq_flags(irq, IRQF_VALID);
390 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
391 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
392 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
393 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
394 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
395 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
396 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
397 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
398 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
402 /*************************************************************************
403 * EP93xx peripheral handling
404 *************************************************************************/
405 #define EP93XX_UART_MCR_OFFSET (0x0100)
407 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
408 void __iomem *base, unsigned int mctrl)
413 if (!(mctrl & TIOCM_RTS))
415 if (!(mctrl & TIOCM_DTR))
418 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
421 static struct amba_pl010_data ep93xx_uart_data = {
422 .set_mctrl = ep93xx_uart_set_mctrl,
425 static struct amba_device uart1_device = {
427 .bus_id = "apb:uart1",
428 .platform_data = &ep93xx_uart_data,
431 .start = EP93XX_UART1_PHYS_BASE,
432 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
433 .flags = IORESOURCE_MEM,
435 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
436 .periphid = 0x00041010,
439 static struct amba_device uart2_device = {
441 .bus_id = "apb:uart2",
442 .platform_data = &ep93xx_uart_data,
445 .start = EP93XX_UART2_PHYS_BASE,
446 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
447 .flags = IORESOURCE_MEM,
449 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
450 .periphid = 0x00041010,
453 static struct amba_device uart3_device = {
455 .bus_id = "apb:uart3",
456 .platform_data = &ep93xx_uart_data,
459 .start = EP93XX_UART3_PHYS_BASE,
460 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
461 .flags = IORESOURCE_MEM,
463 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
464 .periphid = 0x00041010,
468 static struct platform_device ep93xx_rtc_device = {
469 .name = "ep93xx-rtc",
475 static struct resource ep93xx_ohci_resources[] = {
477 .start = EP93XX_USB_PHYS_BASE,
478 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
479 .flags = IORESOURCE_MEM,
482 .start = IRQ_EP93XX_USB,
483 .end = IRQ_EP93XX_USB,
484 .flags = IORESOURCE_IRQ,
488 static struct platform_device ep93xx_ohci_device = {
489 .name = "ep93xx-ohci",
492 .dma_mask = (void *)0xffffffff,
493 .coherent_dma_mask = 0xffffffff,
495 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
496 .resource = ep93xx_ohci_resources,
500 void __init ep93xx_init_devices(void)
505 * Disallow access to MaverickCrunch initially.
507 v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
508 v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
509 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
510 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
512 amba_device_register(&uart1_device, &iomem_resource);
513 amba_device_register(&uart2_device, &iomem_resource);
514 amba_device_register(&uart3_device, &iomem_resource);
516 platform_device_register(&ep93xx_rtc_device);
517 platform_device_register(&ep93xx_ohci_device);