2 * arch/arm/mach-ep93xx/core.c
3 * Core routines for Cirrus EP93xx chips.
5 * Copyright (C) 2006 Lennert Buytenhek <buytenh@wantstofly.org>
7 * Thanks go to Michael Burian and Ray Lehtiniemi for their key
8 * role in the ep93xx linux community.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or (at
13 * your option) any later version.
16 #include <linux/kernel.h>
17 #include <linux/init.h>
18 #include <linux/spinlock.h>
19 #include <linux/sched.h>
20 #include <linux/interrupt.h>
21 #include <linux/serial.h>
22 #include <linux/tty.h>
23 #include <linux/bitops.h>
24 #include <linux/serial.h>
25 #include <linux/serial_8250.h>
26 #include <linux/serial_core.h>
27 #include <linux/device.h>
29 #include <linux/time.h>
30 #include <linux/timex.h>
31 #include <linux/delay.h>
32 #include <linux/termios.h>
33 #include <linux/amba/bus.h>
34 #include <linux/amba/serial.h>
36 #include <asm/types.h>
37 #include <asm/setup.h>
38 #include <asm/memory.h>
39 #include <asm/hardware.h>
41 #include <asm/system.h>
42 #include <asm/tlbflush.h>
43 #include <asm/pgtable.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/time.h>
48 #include <asm/mach/irq.h>
49 #include <asm/arch/gpio.h>
51 #include <asm/hardware/vic.h>
54 /*************************************************************************
55 * Static I/O mappings that are needed for all EP93xx platforms
56 *************************************************************************/
57 static struct map_desc ep93xx_io_desc[] __initdata = {
59 .virtual = EP93XX_AHB_VIRT_BASE,
60 .pfn = __phys_to_pfn(EP93XX_AHB_PHYS_BASE),
61 .length = EP93XX_AHB_SIZE,
64 .virtual = EP93XX_APB_VIRT_BASE,
65 .pfn = __phys_to_pfn(EP93XX_APB_PHYS_BASE),
66 .length = EP93XX_APB_SIZE,
71 void __init ep93xx_map_io(void)
73 iotable_init(ep93xx_io_desc, ARRAY_SIZE(ep93xx_io_desc));
77 /*************************************************************************
78 * Timer handling for EP93xx
79 *************************************************************************
80 * The ep93xx has four internal timers. Timers 1, 2 (both 16 bit) and
81 * 3 (32 bit) count down at 508 kHz, are self-reloading, and can generate
82 * an interrupt on underflow. Timer 4 (40 bit) counts down at 983.04 kHz,
83 * is free-running, and can't generate interrupts.
85 * The 508 kHz timers are ideal for use for the timer interrupt, as the
86 * most common values of HZ divide 508 kHz nicely. We pick one of the 16
87 * bit timers (timer 1) since we don't need more than 16 bits of reload
88 * value as long as HZ >= 8.
90 * The higher clock rate of timer 4 makes it a better choice than the
91 * other timers for use in gettimeoffset(), while the fact that it can't
92 * generate interrupts means we don't have to worry about not being able
93 * to use this timer for something else. We also use timer 4 for keeping
94 * track of lost jiffies.
96 static unsigned int last_jiffy_time;
98 #define TIMER4_TICKS_PER_JIFFY ((CLOCK_TICK_RATE + (HZ/2)) / HZ)
100 static int ep93xx_timer_interrupt(int irq, void *dev_id)
102 __raw_writel(1, EP93XX_TIMER1_CLEAR);
104 (__raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time)
105 >= TIMER4_TICKS_PER_JIFFY) {
106 last_jiffy_time += TIMER4_TICKS_PER_JIFFY;
113 static struct irqaction ep93xx_timer_irq = {
114 .name = "ep93xx timer",
115 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
116 .handler = ep93xx_timer_interrupt,
119 static void __init ep93xx_timer_init(void)
121 /* Enable periodic HZ timer. */
122 __raw_writel(0x48, EP93XX_TIMER1_CONTROL);
123 __raw_writel((508469 / HZ) - 1, EP93XX_TIMER1_LOAD);
124 __raw_writel(0xc8, EP93XX_TIMER1_CONTROL);
126 /* Enable lost jiffy timer. */
127 __raw_writel(0x100, EP93XX_TIMER4_VALUE_HIGH);
129 setup_irq(IRQ_EP93XX_TIMER1, &ep93xx_timer_irq);
132 static unsigned long ep93xx_gettimeoffset(void)
136 offset = __raw_readl(EP93XX_TIMER4_VALUE_LOW) - last_jiffy_time;
138 /* Calculate (1000000 / 983040) * offset. */
139 return offset + (53 * offset / 3072);
142 struct sys_timer ep93xx_timer = {
143 .init = ep93xx_timer_init,
144 .offset = ep93xx_gettimeoffset,
148 /*************************************************************************
149 * GPIO handling for EP93xx
150 *************************************************************************/
151 static unsigned char gpio_int_unmasked[3];
152 static unsigned char gpio_int_enabled[3];
153 static unsigned char gpio_int_type1[3];
154 static unsigned char gpio_int_type2[3];
156 static void update_gpio_int_params(int abf)
159 __raw_writeb(0, EP93XX_GPIO_A_INT_ENABLE);
160 __raw_writeb(gpio_int_type2[0], EP93XX_GPIO_A_INT_TYPE2);
161 __raw_writeb(gpio_int_type1[0], EP93XX_GPIO_A_INT_TYPE1);
162 __raw_writeb(gpio_int_unmasked[0] & gpio_int_enabled[0], EP93XX_GPIO_A_INT_ENABLE);
163 } else if (abf == 1) {
164 __raw_writeb(0, EP93XX_GPIO_B_INT_ENABLE);
165 __raw_writeb(gpio_int_type2[1], EP93XX_GPIO_B_INT_TYPE2);
166 __raw_writeb(gpio_int_type1[1], EP93XX_GPIO_B_INT_TYPE1);
167 __raw_writeb(gpio_int_unmasked[1] & gpio_int_enabled[1], EP93XX_GPIO_B_INT_ENABLE);
168 } else if (abf == 2) {
169 __raw_writeb(0, EP93XX_GPIO_F_INT_ENABLE);
170 __raw_writeb(gpio_int_type2[2], EP93XX_GPIO_F_INT_TYPE2);
171 __raw_writeb(gpio_int_type1[2], EP93XX_GPIO_F_INT_TYPE1);
172 __raw_writeb(gpio_int_unmasked[2] & gpio_int_enabled[2], EP93XX_GPIO_F_INT_ENABLE);
179 static unsigned char data_register_offset[8] = {
180 0x00, 0x04, 0x08, 0x0c, 0x20, 0x30, 0x38, 0x40,
183 static unsigned char data_direction_register_offset[8] = {
184 0x10, 0x14, 0x18, 0x1c, 0x24, 0x34, 0x3c, 0x44,
187 void gpio_line_config(int line, int direction)
189 unsigned int data_direction_register;
193 data_direction_register =
194 EP93XX_GPIO_REG(data_direction_register_offset[line >> 3]);
196 local_irq_save(flags);
197 if (direction == GPIO_OUT) {
198 if (line >= 0 && line < 16) {
200 gpio_int_unmasked[line >> 3] &= ~(1 << (line & 7));
201 update_gpio_int_params(line >> 3);
202 } else if (line >= 40 && line < 48) {
204 gpio_int_unmasked[2] &= ~(1 << (line & 7));
205 update_gpio_int_params(2);
208 v = __raw_readb(data_direction_register);
209 v |= 1 << (line & 7);
210 __raw_writeb(v, data_direction_register);
211 } else if (direction == GPIO_IN) {
212 v = __raw_readb(data_direction_register);
213 v &= ~(1 << (line & 7));
214 __raw_writeb(v, data_direction_register);
216 local_irq_restore(flags);
218 EXPORT_SYMBOL(gpio_line_config);
220 int gpio_line_get(int line)
222 unsigned int data_register;
224 data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
226 return !!(__raw_readb(data_register) & (1 << (line & 7)));
228 EXPORT_SYMBOL(gpio_line_get);
230 void gpio_line_set(int line, int value)
232 unsigned int data_register;
236 data_register = EP93XX_GPIO_REG(data_register_offset[line >> 3]);
238 local_irq_save(flags);
239 if (value == EP93XX_GPIO_HIGH) {
240 v = __raw_readb(data_register);
241 v |= 1 << (line & 7);
242 __raw_writeb(v, data_register);
243 } else if (value == EP93XX_GPIO_LOW) {
244 v = __raw_readb(data_register);
245 v &= ~(1 << (line & 7));
246 __raw_writeb(v, data_register);
248 local_irq_restore(flags);
250 EXPORT_SYMBOL(gpio_line_set);
253 /*************************************************************************
254 * EP93xx IRQ handling
255 *************************************************************************/
256 static void ep93xx_gpio_ab_irq_handler(unsigned int irq, struct irq_desc *desc)
258 unsigned char status;
261 status = __raw_readb(EP93XX_GPIO_A_INT_STATUS);
262 for (i = 0; i < 8; i++) {
263 if (status & (1 << i)) {
264 desc = irq_desc + IRQ_EP93XX_GPIO(0) + i;
265 desc_handle_irq(IRQ_EP93XX_GPIO(0) + i, desc);
269 status = __raw_readb(EP93XX_GPIO_B_INT_STATUS);
270 for (i = 0; i < 8; i++) {
271 if (status & (1 << i)) {
272 desc = irq_desc + IRQ_EP93XX_GPIO(8) + i;
273 desc_handle_irq(IRQ_EP93XX_GPIO(8) + i, desc);
278 static void ep93xx_gpio_f_irq_handler(unsigned int irq, struct irq_desc *desc)
280 int gpio_irq = IRQ_EP93XX_GPIO(16) + (((irq + 1) & 7) ^ 4);
282 desc_handle_irq(gpio_irq, irq_desc + gpio_irq);
285 static void ep93xx_gpio_irq_mask_ack(unsigned int irq)
287 int line = irq - IRQ_EP93XX_GPIO(0);
288 int port = line >> 3;
290 gpio_int_unmasked[port] &= ~(1 << (line & 7));
291 update_gpio_int_params(port);
294 __raw_writel(1 << (line & 7), EP93XX_GPIO_A_INT_ACK);
295 } else if (port == 1) {
296 __raw_writel(1 << (line & 7), EP93XX_GPIO_B_INT_ACK);
297 } else if (port == 2) {
298 __raw_writel(1 << (line & 7), EP93XX_GPIO_F_INT_ACK);
302 static void ep93xx_gpio_irq_mask(unsigned int irq)
304 int line = irq - IRQ_EP93XX_GPIO(0);
305 int port = line >> 3;
307 gpio_int_unmasked[port] &= ~(1 << (line & 7));
308 update_gpio_int_params(port);
311 static void ep93xx_gpio_irq_unmask(unsigned int irq)
313 int line = irq - IRQ_EP93XX_GPIO(0);
314 int port = line >> 3;
316 gpio_int_unmasked[port] |= 1 << (line & 7);
317 update_gpio_int_params(port);
322 * gpio_int_type1 controls whether the interrupt is level (0) or
323 * edge (1) triggered, while gpio_int_type2 controls whether it
324 * triggers on low/falling (0) or high/rising (1).
326 static int ep93xx_gpio_irq_type(unsigned int irq, unsigned int type)
331 line = irq - IRQ_EP93XX_GPIO(0);
332 if (line >= 0 && line < 16) {
333 gpio_line_config(line, GPIO_IN);
335 gpio_line_config(EP93XX_GPIO_LINE_F(line-16), GPIO_IN);
341 if (type & IRQT_RISING) {
342 gpio_int_enabled[port] |= 1 << line;
343 gpio_int_type1[port] |= 1 << line;
344 gpio_int_type2[port] |= 1 << line;
345 } else if (type & IRQT_FALLING) {
346 gpio_int_enabled[port] |= 1 << line;
347 gpio_int_type1[port] |= 1 << line;
348 gpio_int_type2[port] &= ~(1 << line);
349 } else if (type & IRQT_HIGH) {
350 gpio_int_enabled[port] |= 1 << line;
351 gpio_int_type1[port] &= ~(1 << line);
352 gpio_int_type2[port] |= 1 << line;
353 } else if (type & IRQT_LOW) {
354 gpio_int_enabled[port] |= 1 << line;
355 gpio_int_type1[port] &= ~(1 << line);
356 gpio_int_type2[port] &= ~(1 << line);
358 gpio_int_enabled[port] &= ~(1 << line);
360 update_gpio_int_params(port);
365 static struct irq_chip ep93xx_gpio_irq_chip = {
367 .ack = ep93xx_gpio_irq_mask_ack,
368 .mask = ep93xx_gpio_irq_mask,
369 .unmask = ep93xx_gpio_irq_unmask,
370 .set_type = ep93xx_gpio_irq_type,
374 void __init ep93xx_init_irq(void)
378 vic_init((void *)EP93XX_VIC1_BASE, 0, EP93XX_VIC1_VALID_IRQ_MASK);
379 vic_init((void *)EP93XX_VIC2_BASE, 32, EP93XX_VIC2_VALID_IRQ_MASK);
381 for (irq = IRQ_EP93XX_GPIO(0); irq <= IRQ_EP93XX_GPIO(23); irq++) {
382 set_irq_chip(irq, &ep93xx_gpio_irq_chip);
383 set_irq_handler(irq, handle_level_irq);
384 set_irq_flags(irq, IRQF_VALID);
387 set_irq_chained_handler(IRQ_EP93XX_GPIO_AB, ep93xx_gpio_ab_irq_handler);
388 set_irq_chained_handler(IRQ_EP93XX_GPIO0MUX, ep93xx_gpio_f_irq_handler);
389 set_irq_chained_handler(IRQ_EP93XX_GPIO1MUX, ep93xx_gpio_f_irq_handler);
390 set_irq_chained_handler(IRQ_EP93XX_GPIO2MUX, ep93xx_gpio_f_irq_handler);
391 set_irq_chained_handler(IRQ_EP93XX_GPIO3MUX, ep93xx_gpio_f_irq_handler);
392 set_irq_chained_handler(IRQ_EP93XX_GPIO4MUX, ep93xx_gpio_f_irq_handler);
393 set_irq_chained_handler(IRQ_EP93XX_GPIO5MUX, ep93xx_gpio_f_irq_handler);
394 set_irq_chained_handler(IRQ_EP93XX_GPIO6MUX, ep93xx_gpio_f_irq_handler);
395 set_irq_chained_handler(IRQ_EP93XX_GPIO7MUX, ep93xx_gpio_f_irq_handler);
399 /*************************************************************************
400 * EP93xx peripheral handling
401 *************************************************************************/
402 #define EP93XX_UART_MCR_OFFSET (0x0100)
404 static void ep93xx_uart_set_mctrl(struct amba_device *dev,
405 void __iomem *base, unsigned int mctrl)
410 if (!(mctrl & TIOCM_RTS))
412 if (!(mctrl & TIOCM_DTR))
415 __raw_writel(mcr, base + EP93XX_UART_MCR_OFFSET);
418 static struct amba_pl010_data ep93xx_uart_data = {
419 .set_mctrl = ep93xx_uart_set_mctrl,
422 static struct amba_device uart1_device = {
424 .bus_id = "apb:uart1",
425 .platform_data = &ep93xx_uart_data,
428 .start = EP93XX_UART1_PHYS_BASE,
429 .end = EP93XX_UART1_PHYS_BASE + 0x0fff,
430 .flags = IORESOURCE_MEM,
432 .irq = { IRQ_EP93XX_UART1, NO_IRQ },
433 .periphid = 0x00041010,
436 static struct amba_device uart2_device = {
438 .bus_id = "apb:uart2",
439 .platform_data = &ep93xx_uart_data,
442 .start = EP93XX_UART2_PHYS_BASE,
443 .end = EP93XX_UART2_PHYS_BASE + 0x0fff,
444 .flags = IORESOURCE_MEM,
446 .irq = { IRQ_EP93XX_UART2, NO_IRQ },
447 .periphid = 0x00041010,
450 static struct amba_device uart3_device = {
452 .bus_id = "apb:uart3",
453 .platform_data = &ep93xx_uart_data,
456 .start = EP93XX_UART3_PHYS_BASE,
457 .end = EP93XX_UART3_PHYS_BASE + 0x0fff,
458 .flags = IORESOURCE_MEM,
460 .irq = { IRQ_EP93XX_UART3, NO_IRQ },
461 .periphid = 0x00041010,
465 static struct platform_device ep93xx_rtc_device = {
466 .name = "ep93xx-rtc",
472 static struct resource ep93xx_ohci_resources[] = {
474 .start = EP93XX_USB_PHYS_BASE,
475 .end = EP93XX_USB_PHYS_BASE + 0x0fff,
476 .flags = IORESOURCE_MEM,
479 .start = IRQ_EP93XX_USB,
480 .end = IRQ_EP93XX_USB,
481 .flags = IORESOURCE_IRQ,
485 static struct platform_device ep93xx_ohci_device = {
486 .name = "ep93xx-ohci",
489 .dma_mask = (void *)0xffffffff,
490 .coherent_dma_mask = 0xffffffff,
492 .num_resources = ARRAY_SIZE(ep93xx_ohci_resources),
493 .resource = ep93xx_ohci_resources,
497 void __init ep93xx_init_devices(void)
502 * Disallow access to MaverickCrunch initially.
504 v = __raw_readl(EP93XX_SYSCON_DEVICE_CONFIG);
505 v &= ~EP93XX_SYSCON_DEVICE_CONFIG_CRUNCH_ENABLE;
506 __raw_writel(0xaa, EP93XX_SYSCON_SWLOCK);
507 __raw_writel(v, EP93XX_SYSCON_DEVICE_CONFIG);
509 amba_device_register(&uart1_device, &iomem_resource);
510 amba_device_register(&uart2_device, &iomem_resource);
511 amba_device_register(&uart3_device, &iomem_resource);
513 platform_device_register(&ep93xx_rtc_device);
514 platform_device_register(&ep93xx_ohci_device);