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   1 /*
   2  * EDMA3 support for DaVinci
   3  *
   4  * Copyright (C) 2006-2009 Texas Instruments.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19  */
  20 #include <linux/kernel.h>
  21 #include <linux/sched.h>
  22 #include <linux/init.h>
  23 #include <linux/module.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/compiler.h>
  28 #include <linux/io.h>
  29
  30 #include <mach/cputype.h>
  31 #include <mach/memory.h>
  32 #include <mach/hardware.h>
  33 #include <mach/irqs.h>
  34 #include <mach/edma.h>
  35 #include <mach/mux.h>
  36
  37
  38 /* Offsets matching "struct edmacc_param" */
  39 #define PARM_OPT                0x00
  40 #define PARM_SRC                0x04
  41 #define PARM_A_B_CNT            0x08
  42 #define PARM_DST                0x0c
  43 #define PARM_SRC_DST_BIDX       0x10
  44 #define PARM_LINK_BCNTRLD       0x14
  45 #define PARM_SRC_DST_CIDX       0x18
  46 #define PARM_CCNT               0x1c
  47
  48 #define PARM_SIZE               0x20
  49
  50 /* Offsets for EDMA CC global channel registers and their shadows */
  51 #define SH_ER           0x00    /* 64 bits */
  52 #define SH_ECR          0x08    /* 64 bits */
  53 #define SH_ESR          0x10    /* 64 bits */
  54 #define SH_CER          0x18    /* 64 bits */
  55 #define SH_EER          0x20    /* 64 bits */
  56 #define SH_EECR         0x28    /* 64 bits */
  57 #define SH_EESR         0x30    /* 64 bits */
  58 #define SH_SER          0x38    /* 64 bits */
  59 #define SH_SECR         0x40    /* 64 bits */
  60 #define SH_IER          0x50    /* 64 bits */
  61 #define SH_IECR         0x58    /* 64 bits */
  62 #define SH_IESR         0x60    /* 64 bits */
  63 #define SH_IPR          0x68    /* 64 bits */
  64 #define SH_ICR          0x70    /* 64 bits */
  65 #define SH_IEVAL        0x78
  66 #define SH_QER          0x80
  67 #define SH_QEER         0x84
  68 #define SH_QEECR        0x88
  69 #define SH_QEESR        0x8c
  70 #define SH_QSER         0x90
  71 #define SH_QSECR        0x94
  72 #define SH_SIZE         0x200
  73
  74 /* Offsets for EDMA CC global registers */
  75 #define EDMA_REV        0x0000
  76 #define EDMA_CCCFG      0x0004
  77 #define EDMA_QCHMAP     0x0200  /* 8 registers */
  78 #define EDMA_DMAQNUM    0x0240  /* 8 registers (4 on OMAP-L1xx) */
  79 #define EDMA_QDMAQNUM   0x0260
  80 #define EDMA_QUETCMAP   0x0280
  81 #define EDMA_QUEPRI     0x0284
  82 #define EDMA_EMR        0x0300  /* 64 bits */
  83 #define EDMA_EMCR       0x0308  /* 64 bits */
  84 #define EDMA_QEMR       0x0310
  85 #define EDMA_QEMCR      0x0314
  86 #define EDMA_CCERR      0x0318
  87 #define EDMA_CCERRCLR   0x031c
  88 #define EDMA_EEVAL      0x0320
  89 #define EDMA_DRAE       0x0340  /* 4 x 64 bits*/
  90 #define EDMA_QRAE       0x0380  /* 4 registers */
  91 #define EDMA_QUEEVTENTRY        0x0400  /* 2 x 16 registers */
  92 #define EDMA_QSTAT      0x0600  /* 2 registers */
  93 #define EDMA_QWMTHRA    0x0620
  94 #define EDMA_QWMTHRB    0x0624
  95 #define EDMA_CCSTAT     0x0640
  96
  97 #define EDMA_M          0x1000  /* global channel registers */
  98 #define EDMA_ECR        0x1008
  99 #define EDMA_ECRH       0x100C
 100 #define EDMA_SHADOW0    0x2000  /* 4 regions shadowing global channels */
 101 #define EDMA_PARM       0x4000  /* 128 param entries */
 102
 103 #define PARM_OFFSET(param_no)   (EDMA_PARM + ((param_no) << 5))
 104
 105 #define EDMA_DCHMAP     0x0100  /* 64 registers */
 106 #define CHMAP_EXIST     BIT(24)
 107
 108 #define EDMA_MAX_DMACH           64
 109 #define EDMA_MAX_PARAMENTRY     512
 110 #define EDMA_MAX_CC               2
 111
 112
 113 /*****************************************************************************/
 114
 115 static void __iomem *edmacc_regs_base[EDMA_MAX_CC];
 116
 117 static inline unsigned int edma_read(unsigned ctlr, int offset)
 118 {
 119         return (unsigned int)__raw_readl(edmacc_regs_base[ctlr] + offset);
 120 }
 121
 122 static inline void edma_write(unsigned ctlr, int offset, int val)
 123 {
 124         __raw_writel(val, edmacc_regs_base[ctlr] + offset);
 125 }
 126 static inline void edma_modify(unsigned ctlr, int offset, unsigned and,
 127                 unsigned or)
 128 {
 129         unsigned val = edma_read(ctlr, offset);
 130         val &= and;
 131         val |= or;
 132         edma_write(ctlr, offset, val);
 133 }
 134 static inline void edma_and(unsigned ctlr, int offset, unsigned and)
 135 {
 136         unsigned val = edma_read(ctlr, offset);
 137         val &= and;
 138         edma_write(ctlr, offset, val);
 139 }
 140 static inline void edma_or(unsigned ctlr, int offset, unsigned or)
 141 {
 142         unsigned val = edma_read(ctlr, offset);
 143         val |= or;
 144         edma_write(ctlr, offset, val);
 145 }
 146 static inline unsigned int edma_read_array(unsigned ctlr, int offset, int i)
 147 {
 148         return edma_read(ctlr, offset + (i << 2));
 149 }
 150 static inline void edma_write_array(unsigned ctlr, int offset, int i,
 151                 unsigned val)
 152 {
 153         edma_write(ctlr, offset + (i << 2), val);
 154 }
 155 static inline void edma_modify_array(unsigned ctlr, int offset, int i,
 156                 unsigned and, unsigned or)
 157 {
 158         edma_modify(ctlr, offset + (i << 2), and, or);
 159 }
 160 static inline void edma_or_array(unsigned ctlr, int offset, int i, unsigned or)
 161 {
 162         edma_or(ctlr, offset + (i << 2), or);
 163 }
 164 static inline void edma_or_array2(unsigned ctlr, int offset, int i, int j,
 165                 unsigned or)
 166 {
 167         edma_or(ctlr, offset + ((i*2 + j) << 2), or);
 168 }
 169 static inline void edma_write_array2(unsigned ctlr, int offset, int i, int j,
 170                 unsigned val)
 171 {
 172         edma_write(ctlr, offset + ((i*2 + j) << 2), val);
 173 }
 174 static inline unsigned int edma_shadow0_read(unsigned ctlr, int offset)
 175 {
 176         return edma_read(ctlr, EDMA_SHADOW0 + offset);
 177 }
 178 static inline unsigned int edma_shadow0_read_array(unsigned ctlr, int offset,
 179                 int i)
 180 {
 181         return edma_read(ctlr, EDMA_SHADOW0 + offset + (i << 2));
 182 }
 183 static inline void edma_shadow0_write(unsigned ctlr, int offset, unsigned val)
 184 {
 185         edma_write(ctlr, EDMA_SHADOW0 + offset, val);
 186 }
 187 static inline void edma_shadow0_write_array(unsigned ctlr, int offset, int i,
 188                 unsigned val)
 189 {
 190         edma_write(ctlr, EDMA_SHADOW0 + offset + (i << 2), val);
 191 }
 192 static inline unsigned int edma_parm_read(unsigned ctlr, int offset,
 193                 int param_no)
 194 {
 195         return edma_read(ctlr, EDMA_PARM + offset + (param_no << 5));
 196 }
 197 static inline void edma_parm_write(unsigned ctlr, int offset, int param_no,
 198                 unsigned val)
 199 {
 200         edma_write(ctlr, EDMA_PARM + offset + (param_no << 5), val);
 201 }
 202 static inline void edma_parm_modify(unsigned ctlr, int offset, int param_no,
 203                 unsigned and, unsigned or)
 204 {
 205         edma_modify(ctlr, EDMA_PARM + offset + (param_no << 5), and, or);
 206 }
 207 static inline void edma_parm_and(unsigned ctlr, int offset, int param_no,
 208                 unsigned and)
 209 {
 210         edma_and(ctlr, EDMA_PARM + offset + (param_no << 5), and);
 211 }
 212 static inline void edma_parm_or(unsigned ctlr, int offset, int param_no,
 213                 unsigned or)
 214 {
 215         edma_or(ctlr, EDMA_PARM + offset + (param_no << 5), or);
 216 }
 217
 218 /*****************************************************************************/
 219
 220 /* actual number of DMA channels and slots on this silicon */
 221 struct edma {
 222         /* how many dma resources of each type */
 223         unsigned        num_channels;
 224         unsigned        num_region;
 225         unsigned        num_slots;
 226         unsigned        num_tc;
 227         unsigned        num_cc;
 228         enum dma_event_q        default_queue;
 229
 230         /* list of channels with no even trigger; terminated by "-1" */
 231         const s8        *noevent;
 232
 233         /* The edma_inuse bit for each PaRAM slot is clear unless the
 234          * channel is in use ... by ARM or DSP, for QDMA, or whatever.
 235          */
 236         DECLARE_BITMAP(edma_inuse, EDMA_MAX_PARAMENTRY);
 237
 238         /* The edma_noevent bit for each channel is clear unless
 239          * it doesn't trigger DMA events on this platform.  It uses a
 240          * bit of SOC-specific initialization code.
 241          */
 242         DECLARE_BITMAP(edma_noevent, EDMA_MAX_DMACH);
 243
 244         unsigned        irq_res_start;
 245         unsigned        irq_res_end;
 246
 247         struct dma_interrupt_data {
 248                 void (*callback)(unsigned channel, unsigned short ch_status,
 249                                 void *data);
 250                 void *data;
 251         } intr_data[EDMA_MAX_DMACH];
 252 };
 253
 254 static struct edma *edma_info[EDMA_MAX_CC];
 255
 256 /* dummy param set used to (re)initialize parameter RAM slots */
 257 static const struct edmacc_param dummy_paramset = {
 258         .link_bcntrld = 0xffff,
 259         .ccnt = 1,
 260 };
 261
 262 /*****************************************************************************/
 263
 264 static void map_dmach_queue(unsigned ctlr, unsigned ch_no,
 265                 enum dma_event_q queue_no)
 266 {
 267         int bit = (ch_no & 0x7) * 4;
 268
 269         /* default to low priority queue */
 270         if (queue_no == EVENTQ_DEFAULT)
 271                 queue_no = edma_info[ctlr]->default_queue;
 272
 273         queue_no &= 7;
 274         edma_modify_array(ctlr, EDMA_DMAQNUM, (ch_no >> 3),
 275                         ~(0x7 << bit), queue_no << bit);
 276 }
 277
 278 static void __init map_queue_tc(unsigned ctlr, int queue_no, int tc_no)
 279 {
 280         int bit = queue_no * 4;
 281         edma_modify(ctlr, EDMA_QUETCMAP, ~(0x7 << bit), ((tc_no & 0x7) << bit));
 282 }
 283
 284 static void __init assign_priority_to_queue(unsigned ctlr, int queue_no,
 285                 int priority)
 286 {
 287         int bit = queue_no * 4;
 288         edma_modify(ctlr, EDMA_QUEPRI, ~(0x7 << bit),
 289                         ((priority & 0x7) << bit));
 290 }
 291
 292 /**
 293  * map_dmach_param - Maps channel number to param entry number
 294  *
 295  * This maps the dma channel number to param entry numberter. In
 296  * other words using the DMA channel mapping registers a param entry
 297  * can be mapped to any channel
 298  *
 299  * Callers are responsible for ensuring the channel mapping logic is
 300  * included in that particular EDMA variant (Eg : dm646x)
 301  *
 302  */
 303 static void __init map_dmach_param(unsigned ctlr)
 304 {
 305         int i;
 306         for (i = 0; i < EDMA_MAX_DMACH; i++)
 307                 edma_write_array(ctlr, EDMA_DCHMAP , i , (i << 5));
 308 }
 309
 310 static inline void
 311 setup_dma_interrupt(unsigned lch,
 312         void (*callback)(unsigned channel, u16 ch_status, void *data),
 313         void *data)
 314 {
 315         unsigned ctlr;
 316
 317         ctlr = EDMA_CTLR(lch);
 318         lch = EDMA_CHAN_SLOT(lch);
 319
 320         if (!callback) {
 321                 edma_shadow0_write_array(ctlr, SH_IECR, lch >> 5,
 322                                 (1 << (lch & 0x1f)));
 323         }
 324
 325         edma_info[ctlr]->intr_data[lch].callback = callback;
 326         edma_info[ctlr]->intr_data[lch].data = data;
 327
 328         if (callback) {
 329                 edma_shadow0_write_array(ctlr, SH_ICR, lch >> 5,
 330                                 (1 << (lch & 0x1f)));
 331                 edma_shadow0_write_array(ctlr, SH_IESR, lch >> 5,
 332                                 (1 << (lch & 0x1f)));
 333         }
 334 }
 335
 336 static int irq2ctlr(int irq)
 337 {
 338         if (irq >= edma_info[0]->irq_res_start &&
 339                 irq <= edma_info[0]->irq_res_end)
 340                 return 0;
 341         else if (irq >= edma_info[1]->irq_res_start &&
 342                 irq <= edma_info[1]->irq_res_end)
 343                 return 1;
 344
 345         return -1;
 346 }
 347
 348 /******************************************************************************
 349  *
 350  * DMA interrupt handler
 351  *
 352  *****************************************************************************/
 353 static irqreturn_t dma_irq_handler(int irq, void *data)
 354 {
 355         int i;
 356         unsigned ctlr;
 357         unsigned int cnt = 0;
 358
 359         ctlr = irq2ctlr(irq);
 360
 361         dev_dbg(data, "dma_irq_handler\n");
 362
 363         if ((edma_shadow0_read_array(ctlr, SH_IPR, 0) == 0)
 364             && (edma_shadow0_read_array(ctlr, SH_IPR, 1) == 0))
 365                 return IRQ_NONE;
 366
 367         while (1) {
 368                 int j;
 369                 if (edma_shadow0_read_array(ctlr, SH_IPR, 0))
 370                         j = 0;
 371                 else if (edma_shadow0_read_array(ctlr, SH_IPR, 1))
 372                         j = 1;
 373                 else
 374                         break;
 375                 dev_dbg(data, "IPR%d %08x\n", j,
 376                                 edma_shadow0_read_array(ctlr, SH_IPR, j));
 377                 for (i = 0; i < 32; i++) {
 378                         int k = (j << 5) + i;
 379                         if (edma_shadow0_read_array(ctlr, SH_IPR, j) &
 380                                                         (1 << i)) {
 381                                 /* Clear the corresponding IPR bits */
 382                                 edma_shadow0_write_array(ctlr, SH_ICR, j,
 383                                                         (1 << i));
 384                                 if (edma_info[ctlr]->intr_data[k].callback) {
 385                                         edma_info[ctlr]->intr_data[k].callback(
 386                                                 k, DMA_COMPLETE,
 387                                                 edma_info[ctlr]->intr_data[k].
 388                                                 data);
 389                                 }
 390                         }
 391                 }
 392                 cnt++;
 393                 if (cnt > 10)
 394                         break;
 395         }
 396         edma_shadow0_write(ctlr, SH_IEVAL, 1);
 397         return IRQ_HANDLED;
 398 }
 399
 400 /******************************************************************************
 401  *
 402  * DMA error interrupt handler
 403  *
 404  *****************************************************************************/
 405 static irqreturn_t dma_ccerr_handler(int irq, void *data)
 406 {
 407         int i;
 408         unsigned ctlr;
 409         unsigned int cnt = 0;
 410
 411         ctlr = irq2ctlr(irq);
 412
 413         dev_dbg(data, "dma_ccerr_handler\n");
 414
 415         if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0) &&
 416             (edma_read_array(ctlr, EDMA_EMR, 1) == 0) &&
 417             (edma_read(ctlr, EDMA_QEMR) == 0) &&
 418             (edma_read(ctlr, EDMA_CCERR) == 0))
 419                 return IRQ_NONE;
 420
 421         while (1) {
 422                 int j = -1;
 423                 if (edma_read_array(ctlr, EDMA_EMR, 0))
 424                         j = 0;
 425                 else if (edma_read_array(ctlr, EDMA_EMR, 1))
 426                         j = 1;
 427                 if (j >= 0) {
 428                         dev_dbg(data, "EMR%d %08x\n", j,
 429                                         edma_read_array(ctlr, EDMA_EMR, j));
 430                         for (i = 0; i < 32; i++) {
 431                                 int k = (j << 5) + i;
 432                                 if (edma_read_array(ctlr, EDMA_EMR, j) &
 433                                                         (1 << i)) {
 434                                         /* Clear the corresponding EMR bits */
 435                                         edma_write_array(ctlr, EDMA_EMCR, j,
 436                                                         1 << i);
 437                                         /* Clear any SER */
 438                                         edma_shadow0_write_array(ctlr, SH_SECR,
 439                                                                 j, (1 << i));
 440                                         if (edma_info[ctlr]->intr_data[k].
 441                                                                 callback) {
 442                                                 edma_info[ctlr]->intr_data[k].
 443                                                 callback(k,
 444                                                 DMA_CC_ERROR,
 445                                                 edma_info[ctlr]->intr_data
 446                                                 [k].data);
 447                                         }
 448                                 }
 449                         }
 450                 } else if (edma_read(ctlr, EDMA_QEMR)) {
 451                         dev_dbg(data, "QEMR %02x\n",
 452                                 edma_read(ctlr, EDMA_QEMR));
 453                         for (i = 0; i < 8; i++) {
 454                                 if (edma_read(ctlr, EDMA_QEMR) & (1 << i)) {
 455                                         /* Clear the corresponding IPR bits */
 456                                         edma_write(ctlr, EDMA_QEMCR, 1 << i);
 457                                         edma_shadow0_write(ctlr, SH_QSECR,
 458                                                                 (1 << i));
 459
 460                                         /* NOTE:  not reported!! */
 461                                 }
 462                         }
 463                 } else if (edma_read(ctlr, EDMA_CCERR)) {
 464                         dev_dbg(data, "CCERR %08x\n",
 465                                 edma_read(ctlr, EDMA_CCERR));
 466                         /* FIXME:  CCERR.BIT(16) ignored!  much better
 467                          * to just write CCERRCLR with CCERR value...
 468                          */
 469                         for (i = 0; i < 8; i++) {
 470                                 if (edma_read(ctlr, EDMA_CCERR) & (1 << i)) {
 471                                         /* Clear the corresponding IPR bits */
 472                                         edma_write(ctlr, EDMA_CCERRCLR, 1 << i);
 473
 474                                         /* NOTE:  not reported!! */
 475                                 }
 476                         }
 477                 }
 478                 if ((edma_read_array(ctlr, EDMA_EMR, 0) == 0)
 479                     && (edma_read_array(ctlr, EDMA_EMR, 1) == 0)
 480                     && (edma_read(ctlr, EDMA_QEMR) == 0)
 481                     && (edma_read(ctlr, EDMA_CCERR) == 0)) {
 482                         break;
 483                 }
 484                 cnt++;
 485                 if (cnt > 10)
 486                         break;
 487         }
 488         edma_write(ctlr, EDMA_EEVAL, 1);
 489         return IRQ_HANDLED;
 490 }
 491
 492 /******************************************************************************
 493  *
 494  * Transfer controller error interrupt handlers
 495  *
 496  *****************************************************************************/
 497
 498 #define tc_errs_handled false   /* disabled as long as they're NOPs */
 499
 500 static irqreturn_t dma_tc0err_handler(int irq, void *data)
 501 {
 502         dev_dbg(data, "dma_tc0err_handler\n");
 503         return IRQ_HANDLED;
 504 }
 505
 506 static irqreturn_t dma_tc1err_handler(int irq, void *data)
 507 {
 508         dev_dbg(data, "dma_tc1err_handler\n");
 509         return IRQ_HANDLED;
 510 }
 511
 512 /*-----------------------------------------------------------------------*/
 513
 514 /* Resource alloc/free:  dma channels, parameter RAM slots */
 515
 516 /**
 517  * edma_alloc_channel - allocate DMA channel and paired parameter RAM
 518  * @channel: specific channel to allocate; negative for "any unmapped channel"
 519  * @callback: optional; to be issued on DMA completion or errors
 520  * @data: passed to callback
 521  * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
 522  *      Controller (TC) executes requests using this channel.  Use
 523  *      EVENTQ_DEFAULT unless you really need a high priority queue.
 524  *
 525  * This allocates a DMA channel and its associated parameter RAM slot.
 526  * The parameter RAM is initialized to hold a dummy transfer.
 527  *
 528  * Normal use is to pass a specific channel number as @channel, to make
 529  * use of hardware events mapped to that channel.  When the channel will
 530  * be used only for software triggering or event chaining, channels not
 531  * mapped to hardware events (or mapped to unused events) are preferable.
 532  *
 533  * DMA transfers start from a channel using edma_start(), or by
 534  * chaining.  When the transfer described in that channel's parameter RAM
 535  * slot completes, that slot's data may be reloaded through a link.
 536  *
 537  * DMA errors are only reported to the @callback associated with the
 538  * channel driving that transfer, but transfer completion callbacks can
 539  * be sent to another channel under control of the TCC field in
 540  * the option word of the transfer's parameter RAM set.  Drivers must not
 541  * use DMA transfer completion callbacks for channels they did not allocate.
 542  * (The same applies to TCC codes used in transfer chaining.)
 543  *
 544  * Returns the number of the channel, else negative errno.
 545  */
 546 int edma_alloc_channel(int channel,
 547                 void (*callback)(unsigned channel, u16 ch_status, void *data),
 548                 void *data,
 549                 enum dma_event_q eventq_no)
 550 {
 551         unsigned i, done, ctlr = 0;
 552
 553         if (channel >= 0) {
 554                 ctlr = EDMA_CTLR(channel);
 555                 channel = EDMA_CHAN_SLOT(channel);
 556         }
 557
 558         if (channel < 0) {
 559                 for (i = 0; i < EDMA_MAX_CC; i++) {
 560                         channel = 0;
 561                         for (;;) {
 562                                 channel = find_next_bit(edma_info[i]->
 563                                                 edma_noevent,
 564                                                 edma_info[i]->num_channels,
 565                                                 channel);
 566                                 if (channel == edma_info[i]->num_channels)
 567                                         return -ENOMEM;
 568                                 if (!test_and_set_bit(channel,
 569                                                 edma_info[i]->edma_inuse)) {
 570                                         done = 1;
 571                                         ctlr = i;
 572                                         break;
 573                                 }
 574                                 channel++;
 575                         }
 576                         if (done)
 577                                 break;
 578                 }
 579         } else if (channel >= edma_info[ctlr]->num_channels) {
 580                 return -EINVAL;
 581         } else if (test_and_set_bit(channel, edma_info[ctlr]->edma_inuse)) {
 582                 return -EBUSY;
 583         }
 584
 585         /* ensure access through shadow region 0 */
 586         edma_or_array2(ctlr, EDMA_DRAE, 0, channel >> 5, 1 << (channel & 0x1f));
 587
 588         /* ensure no events are pending */
 589         edma_stop(EDMA_CTLR_CHAN(ctlr, channel));
 590         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
 591                         &dummy_paramset, PARM_SIZE);
 592
 593         if (callback)
 594                 setup_dma_interrupt(EDMA_CTLR_CHAN(ctlr, channel),
 595                                         callback, data);
 596
 597         map_dmach_queue(ctlr, channel, eventq_no);
 598
 599         return channel;
 600 }
 601 EXPORT_SYMBOL(edma_alloc_channel);
 602
 603
 604 /**
 605  * edma_free_channel - deallocate DMA channel
 606  * @channel: dma channel returned from edma_alloc_channel()
 607  *
 608  * This deallocates the DMA channel and associated parameter RAM slot
 609  * allocated by edma_alloc_channel().
 610  *
 611  * Callers are responsible for ensuring the channel is inactive, and
 612  * will not be reactivated by linking, chaining, or software calls to
 613  * edma_start().
 614  */
 615 void edma_free_channel(unsigned channel)
 616 {
 617         unsigned ctlr;
 618
 619         ctlr = EDMA_CTLR(channel);
 620         channel = EDMA_CHAN_SLOT(channel);
 621
 622         if (channel >= edma_info[ctlr]->num_channels)
 623                 return;
 624
 625         setup_dma_interrupt(channel, NULL, NULL);
 626         /* REVISIT should probably take out of shadow region 0 */
 627
 628         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(channel),
 629                         &dummy_paramset, PARM_SIZE);
 630         clear_bit(channel, edma_info[ctlr]->edma_inuse);
 631 }
 632 EXPORT_SYMBOL(edma_free_channel);
 633
 634 /**
 635  * edma_alloc_slot - allocate DMA parameter RAM
 636  * @slot: specific slot to allocate; negative for "any unused slot"
 637  *
 638  * This allocates a parameter RAM slot, initializing it to hold a
 639  * dummy transfer.  Slots allocated using this routine have not been
 640  * mapped to a hardware DMA channel, and will normally be used by
 641  * linking to them from a slot associated with a DMA channel.
 642  *
 643  * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
 644  * slots may be allocated on behalf of DSP firmware.
 645  *
 646  * Returns the number of the slot, else negative errno.
 647  */
 648 int edma_alloc_slot(unsigned ctlr, int slot)
 649 {
 650         if (slot >= 0)
 651                 slot = EDMA_CHAN_SLOT(slot);
 652
 653         if (slot < 0) {
 654                 slot = edma_info[ctlr]->num_channels;
 655                 for (;;) {
 656                         slot = find_next_zero_bit(edma_info[ctlr]->edma_inuse,
 657                                         edma_info[ctlr]->num_slots, slot);
 658                         if (slot == edma_info[ctlr]->num_slots)
 659                                 return -ENOMEM;
 660                         if (!test_and_set_bit(slot,
 661                                                 edma_info[ctlr]->edma_inuse))
 662                                 break;
 663                 }
 664         } else if (slot < edma_info[ctlr]->num_channels ||
 665                         slot >= edma_info[ctlr]->num_slots) {
 666                 return -EINVAL;
 667         } else if (test_and_set_bit(slot, edma_info[ctlr]->edma_inuse)) {
 668                 return -EBUSY;
 669         }
 670
 671         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
 672                         &dummy_paramset, PARM_SIZE);
 673
 674         return EDMA_CTLR_CHAN(ctlr, slot);
 675 }
 676 EXPORT_SYMBOL(edma_alloc_slot);
 677
 678 /**
 679  * edma_free_slot - deallocate DMA parameter RAM
 680  * @slot: parameter RAM slot returned from edma_alloc_slot()
 681  *
 682  * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
 683  * Callers are responsible for ensuring the slot is inactive, and will
 684  * not be activated.
 685  */
 686 void edma_free_slot(unsigned slot)
 687 {
 688         unsigned ctlr;
 689
 690         ctlr = EDMA_CTLR(slot);
 691         slot = EDMA_CHAN_SLOT(slot);
 692
 693         if (slot < edma_info[ctlr]->num_channels ||
 694                 slot >= edma_info[ctlr]->num_slots)
 695                 return;
 696
 697         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
 698                         &dummy_paramset, PARM_SIZE);
 699         clear_bit(slot, edma_info[ctlr]->edma_inuse);
 700 }
 701 EXPORT_SYMBOL(edma_free_slot);
 702
 703 /*-----------------------------------------------------------------------*/
 704
 705 /* Parameter RAM operations (i) -- read/write partial slots */
 706
 707 /**
 708  * edma_set_src - set initial DMA source address in parameter RAM slot
 709  * @slot: parameter RAM slot being configured
 710  * @src_port: physical address of source (memory, controller FIFO, etc)
 711  * @addressMode: INCR, except in very rare cases
 712  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
 713  *      width to use when addressing the fifo (e.g. W8BIT, W32BIT)
 714  *
 715  * Note that the source address is modified during the DMA transfer
 716  * according to edma_set_src_index().
 717  */
 718 void edma_set_src(unsigned slot, dma_addr_t src_port,
 719                                 enum address_mode mode, enum fifo_width width)
 720 {
 721         unsigned ctlr;
 722
 723         ctlr = EDMA_CTLR(slot);
 724         slot = EDMA_CHAN_SLOT(slot);
 725
 726         if (slot < edma_info[ctlr]->num_slots) {
 727                 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 728
 729                 if (mode) {
 730                         /* set SAM and program FWID */
 731                         i = (i & ~(EDMA_FWID)) | (SAM | ((width & 0x7) << 8));
 732                 } else {
 733                         /* clear SAM */
 734                         i &= ~SAM;
 735                 }
 736                 edma_parm_write(ctlr, PARM_OPT, slot, i);
 737
 738                 /* set the source port address
 739                    in source register of param structure */
 740                 edma_parm_write(ctlr, PARM_SRC, slot, src_port);
 741         }
 742 }
 743 EXPORT_SYMBOL(edma_set_src);
 744
 745 /**
 746  * edma_set_dest - set initial DMA destination address in parameter RAM slot
 747  * @slot: parameter RAM slot being configured
 748  * @dest_port: physical address of destination (memory, controller FIFO, etc)
 749  * @addressMode: INCR, except in very rare cases
 750  * @fifoWidth: ignored unless @addressMode is FIFO, else specifies the
 751  *      width to use when addressing the fifo (e.g. W8BIT, W32BIT)
 752  *
 753  * Note that the destination address is modified during the DMA transfer
 754  * according to edma_set_dest_index().
 755  */
 756 void edma_set_dest(unsigned slot, dma_addr_t dest_port,
 757                                  enum address_mode mode, enum fifo_width width)
 758 {
 759         unsigned ctlr;
 760
 761         ctlr = EDMA_CTLR(slot);
 762         slot = EDMA_CHAN_SLOT(slot);
 763
 764         if (slot < edma_info[ctlr]->num_slots) {
 765                 unsigned int i = edma_parm_read(ctlr, PARM_OPT, slot);
 766
 767                 if (mode) {
 768                         /* set DAM and program FWID */
 769                         i = (i & ~(EDMA_FWID)) | (DAM | ((width & 0x7) << 8));
 770                 } else {
 771                         /* clear DAM */
 772                         i &= ~DAM;
 773                 }
 774                 edma_parm_write(ctlr, PARM_OPT, slot, i);
 775                 /* set the destination port address
 776                    in dest register of param structure */
 777                 edma_parm_write(ctlr, PARM_DST, slot, dest_port);
 778         }
 779 }
 780 EXPORT_SYMBOL(edma_set_dest);
 781
 782 /**
 783  * edma_get_position - returns the current transfer points
 784  * @slot: parameter RAM slot being examined
 785  * @src: pointer to source port position
 786  * @dst: pointer to destination port position
 787  *
 788  * Returns current source and destination addresses for a particular
 789  * parameter RAM slot.  Its channel should not be active when this is called.
 790  */
 791 void edma_get_position(unsigned slot, dma_addr_t *src, dma_addr_t *dst)
 792 {
 793         struct edmacc_param temp;
 794         unsigned ctlr;
 795
 796         ctlr = EDMA_CTLR(slot);
 797         slot = EDMA_CHAN_SLOT(slot);
 798
 799         edma_read_slot(EDMA_CTLR_CHAN(ctlr, slot), &temp);
 800         if (src != NULL)
 801                 *src = temp.src;
 802         if (dst != NULL)
 803                 *dst = temp.dst;
 804 }
 805 EXPORT_SYMBOL(edma_get_position);
 806
 807 /**
 808  * edma_set_src_index - configure DMA source address indexing
 809  * @slot: parameter RAM slot being configured
 810  * @src_bidx: byte offset between source arrays in a frame
 811  * @src_cidx: byte offset between source frames in a block
 812  *
 813  * Offsets are specified to support either contiguous or discontiguous
 814  * memory transfers, or repeated access to a hardware register, as needed.
 815  * When accessing hardware registers, both offsets are normally zero.
 816  */
 817 void edma_set_src_index(unsigned slot, s16 src_bidx, s16 src_cidx)
 818 {
 819         unsigned ctlr;
 820
 821         ctlr = EDMA_CTLR(slot);
 822         slot = EDMA_CHAN_SLOT(slot);
 823
 824         if (slot < edma_info[ctlr]->num_slots) {
 825                 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
 826                                 0xffff0000, src_bidx);
 827                 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
 828                                 0xffff0000, src_cidx);
 829         }
 830 }
 831 EXPORT_SYMBOL(edma_set_src_index);
 832
 833 /**
 834  * edma_set_dest_index - configure DMA destination address indexing
 835  * @slot: parameter RAM slot being configured
 836  * @dest_bidx: byte offset between destination arrays in a frame
 837  * @dest_cidx: byte offset between destination frames in a block
 838  *
 839  * Offsets are specified to support either contiguous or discontiguous
 840  * memory transfers, or repeated access to a hardware register, as needed.
 841  * When accessing hardware registers, both offsets are normally zero.
 842  */
 843 void edma_set_dest_index(unsigned slot, s16 dest_bidx, s16 dest_cidx)
 844 {
 845         unsigned ctlr;
 846
 847         ctlr = EDMA_CTLR(slot);
 848         slot = EDMA_CHAN_SLOT(slot);
 849
 850         if (slot < edma_info[ctlr]->num_slots) {
 851                 edma_parm_modify(ctlr, PARM_SRC_DST_BIDX, slot,
 852                                 0x0000ffff, dest_bidx << 16);
 853                 edma_parm_modify(ctlr, PARM_SRC_DST_CIDX, slot,
 854                                 0x0000ffff, dest_cidx << 16);
 855         }
 856 }
 857 EXPORT_SYMBOL(edma_set_dest_index);
 858
 859 /**
 860  * edma_set_transfer_params - configure DMA transfer parameters
 861  * @slot: parameter RAM slot being configured
 862  * @acnt: how many bytes per array (at least one)
 863  * @bcnt: how many arrays per frame (at least one)
 864  * @ccnt: how many frames per block (at least one)
 865  * @bcnt_rld: used only for A-Synchronized transfers; this specifies
 866  *      the value to reload into bcnt when it decrements to zero
 867  * @sync_mode: ASYNC or ABSYNC
 868  *
 869  * See the EDMA3 documentation to understand how to configure and link
 870  * transfers using the fields in PaRAM slots.  If you are not doing it
 871  * all at once with edma_write_slot(), you will use this routine
 872  * plus two calls each for source and destination, setting the initial
 873  * address and saying how to index that address.
 874  *
 875  * An example of an A-Synchronized transfer is a serial link using a
 876  * single word shift register.  In that case, @acnt would be equal to
 877  * that word size; the serial controller issues a DMA synchronization
 878  * event to transfer each word, and memory access by the DMA transfer
 879  * controller will be word-at-a-time.
 880  *
 881  * An example of an AB-Synchronized transfer is a device using a FIFO.
 882  * In that case, @acnt equals the FIFO width and @bcnt equals its depth.
 883  * The controller with the FIFO issues DMA synchronization events when
 884  * the FIFO threshold is reached, and the DMA transfer controller will
 885  * transfer one frame to (or from) the FIFO.  It will probably use
 886  * efficient burst modes to access memory.
 887  */
 888 void edma_set_transfer_params(unsigned slot,
 889                 u16 acnt, u16 bcnt, u16 ccnt,
 890                 u16 bcnt_rld, enum sync_dimension sync_mode)
 891 {
 892         unsigned ctlr;
 893
 894         ctlr = EDMA_CTLR(slot);
 895         slot = EDMA_CHAN_SLOT(slot);
 896
 897         if (slot < edma_info[ctlr]->num_slots) {
 898                 edma_parm_modify(ctlr, PARM_LINK_BCNTRLD, slot,
 899                                 0x0000ffff, bcnt_rld << 16);
 900                 if (sync_mode == ASYNC)
 901                         edma_parm_and(ctlr, PARM_OPT, slot, ~SYNCDIM);
 902                 else
 903                         edma_parm_or(ctlr, PARM_OPT, slot, SYNCDIM);
 904                 /* Set the acount, bcount, ccount registers */
 905                 edma_parm_write(ctlr, PARM_A_B_CNT, slot, (bcnt << 16) | acnt);
 906                 edma_parm_write(ctlr, PARM_CCNT, slot, ccnt);
 907         }
 908 }
 909 EXPORT_SYMBOL(edma_set_transfer_params);
 910
 911 /**
 912  * edma_link - link one parameter RAM slot to another
 913  * @from: parameter RAM slot originating the link
 914  * @to: parameter RAM slot which is the link target
 915  *
 916  * The originating slot should not be part of any active DMA transfer.
 917  */
 918 void edma_link(unsigned from, unsigned to)
 919 {
 920         unsigned ctlr_from, ctlr_to;
 921
 922         ctlr_from = EDMA_CTLR(from);
 923         from = EDMA_CHAN_SLOT(from);
 924         ctlr_to = EDMA_CTLR(to);
 925         to = EDMA_CHAN_SLOT(to);
 926
 927         if (from >= edma_info[ctlr_from]->num_slots)
 928                 return;
 929         if (to >= edma_info[ctlr_to]->num_slots)
 930                 return;
 931         edma_parm_modify(ctlr_from, PARM_LINK_BCNTRLD, from, 0xffff0000,
 932                                 PARM_OFFSET(to));
 933 }
 934 EXPORT_SYMBOL(edma_link);
 935
 936 /**
 937  * edma_unlink - cut link from one parameter RAM slot
 938  * @from: parameter RAM slot originating the link
 939  *
 940  * The originating slot should not be part of any active DMA transfer.
 941  * Its link is set to 0xffff.
 942  */
 943 void edma_unlink(unsigned from)
 944 {
 945         unsigned ctlr;
 946
 947         ctlr = EDMA_CTLR(from);
 948         from = EDMA_CHAN_SLOT(from);
 949
 950         if (from >= edma_info[ctlr]->num_slots)
 951                 return;
 952         edma_parm_or(ctlr, PARM_LINK_BCNTRLD, from, 0xffff);
 953 }
 954 EXPORT_SYMBOL(edma_unlink);
 955
 956 /*-----------------------------------------------------------------------*/
 957
 958 /* Parameter RAM operations (ii) -- read/write whole parameter sets */
 959
 960 /**
 961  * edma_write_slot - write parameter RAM data for slot
 962  * @slot: number of parameter RAM slot being modified
 963  * @param: data to be written into parameter RAM slot
 964  *
 965  * Use this to assign all parameters of a transfer at once.  This
 966  * allows more efficient setup of transfers than issuing multiple
 967  * calls to set up those parameters in small pieces, and provides
 968  * complete control over all transfer options.
 969  */
 970 void edma_write_slot(unsigned slot, const struct edmacc_param *param)
 971 {
 972         unsigned ctlr;
 973
 974         ctlr = EDMA_CTLR(slot);
 975         slot = EDMA_CHAN_SLOT(slot);
 976
 977         if (slot >= edma_info[ctlr]->num_slots)
 978                 return;
 979         memcpy_toio(edmacc_regs_base[ctlr] + PARM_OFFSET(slot), param,
 980                         PARM_SIZE);
 981 }
 982 EXPORT_SYMBOL(edma_write_slot);
 983
 984 /**
 985  * edma_read_slot - read parameter RAM data from slot
 986  * @slot: number of parameter RAM slot being copied
 987  * @param: where to store copy of parameter RAM data
 988  *
 989  * Use this to read data from a parameter RAM slot, perhaps to
 990  * save them as a template for later reuse.
 991  */
 992 void edma_read_slot(unsigned slot, struct edmacc_param *param)
 993 {
 994         unsigned ctlr;
 995
 996         ctlr = EDMA_CTLR(slot);
 997         slot = EDMA_CHAN_SLOT(slot);
 998
 999         if (slot >= edma_info[ctlr]->num_slots)
1000                 return;
1001         memcpy_fromio(param, edmacc_regs_base[ctlr] + PARM_OFFSET(slot),
1002                         PARM_SIZE);
1003 }
1004 EXPORT_SYMBOL(edma_read_slot);
1005
1006 /*-----------------------------------------------------------------------*/
1007
1008 /* Various EDMA channel control operations */
1009
1010 /**
1011  * edma_pause - pause dma on a channel
1012  * @channel: on which edma_start() has been called
1013  *
1014  * This temporarily disables EDMA hardware events on the specified channel,
1015  * preventing them from triggering new transfers on its behalf
1016  */
1017 void edma_pause(unsigned channel)
1018 {
1019         unsigned ctlr;
1020
1021         ctlr = EDMA_CTLR(channel);
1022         channel = EDMA_CHAN_SLOT(channel);
1023
1024         if (channel < edma_info[ctlr]->num_channels) {
1025                 unsigned int mask = (1 << (channel & 0x1f));
1026
1027                 edma_shadow0_write_array(ctlr, SH_EECR, channel >> 5, mask);
1028         }
1029 }
1030 EXPORT_SYMBOL(edma_pause);
1031
1032 /**
1033  * edma_resume - resumes dma on a paused channel
1034  * @channel: on which edma_pause() has been called
1035  *
1036  * This re-enables EDMA hardware events on the specified channel.
1037  */
1038 void edma_resume(unsigned channel)
1039 {
1040         unsigned ctlr;
1041
1042         ctlr = EDMA_CTLR(channel);
1043         channel = EDMA_CHAN_SLOT(channel);
1044
1045         if (channel < edma_info[ctlr]->num_channels) {
1046                 unsigned int mask = (1 << (channel & 0x1f));
1047
1048                 edma_shadow0_write_array(ctlr, SH_EESR, channel >> 5, mask);
1049         }
1050 }
1051 EXPORT_SYMBOL(edma_resume);
1052
1053 /**
1054  * edma_start - start dma on a channel
1055  * @channel: channel being activated
1056  *
1057  * Channels with event associations will be triggered by their hardware
1058  * events, and channels without such associations will be triggered by
1059  * software.  (At this writing there is no interface for using software
1060  * triggers except with channels that don't support hardware triggers.)
1061  *
1062  * Returns zero on success, else negative errno.
1063  */
1064 int edma_start(unsigned channel)
1065 {
1066         unsigned ctlr;
1067
1068         ctlr = EDMA_CTLR(channel);
1069         channel = EDMA_CHAN_SLOT(channel);
1070
1071         if (channel < edma_info[ctlr]->num_channels) {
1072                 int j = channel >> 5;
1073                 unsigned int mask = (1 << (channel & 0x1f));
1074
1075                 /* EDMA channels without event association */
1076                 if (test_bit(channel, edma_info[ctlr]->edma_noevent)) {
1077                         pr_debug("EDMA: ESR%d %08x\n", j,
1078                                 edma_shadow0_read_array(ctlr, SH_ESR, j));
1079                         edma_shadow0_write_array(ctlr, SH_ESR, j, mask);
1080                         return 0;
1081                 }
1082
1083                 /* EDMA channel with event association */
1084                 pr_debug("EDMA: ER%d %08x\n", j,
1085                         edma_shadow0_read_array(ctlr, SH_ER, j));
1086                 /* Clear any pending error */
1087                 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1088                 /* Clear any SER */
1089                 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1090                 edma_shadow0_write_array(ctlr, SH_EESR, j, mask);
1091                 pr_debug("EDMA: EER%d %08x\n", j,
1092                         edma_shadow0_read_array(ctlr, SH_EER, j));
1093                 return 0;
1094         }
1095
1096         return -EINVAL;
1097 }
1098 EXPORT_SYMBOL(edma_start);
1099
1100 /**
1101  * edma_stop - stops dma on the channel passed
1102  * @channel: channel being deactivated
1103  *
1104  * When @lch is a channel, any active transfer is paused and
1105  * all pending hardware events are cleared.  The current transfer
1106  * may not be resumed, and the channel's Parameter RAM should be
1107  * reinitialized before being reused.
1108  */
1109 void edma_stop(unsigned channel)
1110 {
1111         unsigned ctlr;
1112
1113         ctlr = EDMA_CTLR(channel);
1114         channel = EDMA_CHAN_SLOT(channel);
1115
1116         if (channel < edma_info[ctlr]->num_channels) {
1117                 int j = channel >> 5;
1118                 unsigned int mask = (1 << (channel & 0x1f));
1119
1120                 edma_shadow0_write_array(ctlr, SH_EECR, j, mask);
1121                 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1122                 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1123                 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1124
1125                 pr_debug("EDMA: EER%d %08x\n", j,
1126                                 edma_shadow0_read_array(ctlr, SH_EER, j));
1127
1128                 /* REVISIT:  consider guarding against inappropriate event
1129                  * chaining by overwriting with dummy_paramset.
1130                  */
1131         }
1132 }
1133 EXPORT_SYMBOL(edma_stop);
1134
1135 /******************************************************************************
1136  *
1137  * It cleans ParamEntry qand bring back EDMA to initial state if media has
1138  * been removed before EDMA has finished.It is usedful for removable media.
1139  * Arguments:
1140  *      ch_no     - channel no
1141  *
1142  * Return: zero on success, or corresponding error no on failure
1143  *
1144  * FIXME this should not be needed ... edma_stop() should suffice.
1145  *
1146  *****************************************************************************/
1147
1148 void edma_clean_channel(unsigned channel)
1149 {
1150         unsigned ctlr;
1151
1152         ctlr = EDMA_CTLR(channel);
1153         channel = EDMA_CHAN_SLOT(channel);
1154
1155         if (channel < edma_info[ctlr]->num_channels) {
1156                 int j = (channel >> 5);
1157                 unsigned int mask = 1 << (channel & 0x1f);
1158
1159                 pr_debug("EDMA: EMR%d %08x\n", j,
1160                                 edma_read_array(ctlr, EDMA_EMR, j));
1161                 edma_shadow0_write_array(ctlr, SH_ECR, j, mask);
1162                 /* Clear the corresponding EMR bits */
1163                 edma_write_array(ctlr, EDMA_EMCR, j, mask);
1164                 /* Clear any SER */
1165                 edma_shadow0_write_array(ctlr, SH_SECR, j, mask);
1166                 edma_write(ctlr, EDMA_CCERRCLR, (1 << 16) | 0x3);
1167         }
1168 }
1169 EXPORT_SYMBOL(edma_clean_channel);
1170
1171 /*
1172  * edma_clear_event - clear an outstanding event on the DMA channel
1173  * Arguments:
1174  *      channel - channel number
1175  */
1176 void edma_clear_event(unsigned channel)
1177 {
1178         unsigned ctlr;
1179
1180         ctlr = EDMA_CTLR(channel);
1181         channel = EDMA_CHAN_SLOT(channel);
1182
1183         if (channel >= edma_info[ctlr]->num_channels)
1184                 return;
1185         if (channel < 32)
1186                 edma_write(ctlr, EDMA_ECR, 1 << channel);
1187         else
1188                 edma_write(ctlr, EDMA_ECRH, 1 << (channel - 32));
1189 }
1190 EXPORT_SYMBOL(edma_clear_event);
1191
1192 /*-----------------------------------------------------------------------*/
1193
1194 static int __init edma_probe(struct platform_device *pdev)
1195 {
1196         struct edma_soc_info    *info = pdev->dev.platform_data;
1197         const s8                (*queue_priority_mapping)[2];
1198         const s8                (*queue_tc_mapping)[2];
1199         int                     i, j, found = 0;
1200         int                     status = -1;
1201         const s8                *noevent;
1202         int                     irq[EDMA_MAX_CC] = {0, 0};
1203         int                     err_irq[EDMA_MAX_CC] = {0, 0};
1204         struct resource         *r[EDMA_MAX_CC] = {NULL};
1205         resource_size_t         len[EDMA_MAX_CC];
1206         char                    res_name[10];
1207         char                    irq_name[10];
1208
1209         if (!info)
1210                 return -ENODEV;
1211
1212         for (j = 0; j < EDMA_MAX_CC; j++) {
1213                 sprintf(res_name, "edma_cc%d", j);
1214                 r[j] = platform_get_resource_byname(pdev, IORESOURCE_MEM,
1215                                                 res_name);
1216                 if (!r[j]) {
1217                         if (found)
1218                                 break;
1219                         else
1220                                 return -ENODEV;
1221                 } else
1222                         found = 1;
1223
1224                 len[j] = resource_size(r[j]);
1225
1226                 r[j] = request_mem_region(r[j]->start, len[j],
1227                         dev_name(&pdev->dev));
1228                 if (!r[j]) {
1229                         status = -EBUSY;
1230                         goto fail1;
1231                 }
1232
1233                 edmacc_regs_base[j] = ioremap(r[j]->start, len[j]);
1234                 if (!edmacc_regs_base[j]) {
1235                         status = -EBUSY;
1236                         goto fail1;
1237                 }
1238
1239                 edma_info[j] = kmalloc(sizeof(struct edma), GFP_KERNEL);
1240                 if (!edma_info[j]) {
1241                         status = -ENOMEM;
1242                         goto fail1;
1243                 }
1244                 memset(edma_info[j], 0, sizeof(struct edma));
1245
1246                 edma_info[j]->num_channels = min_t(unsigned, info[j].n_channel,
1247                                                         EDMA_MAX_DMACH);
1248                 edma_info[j]->num_slots = min_t(unsigned, info[j].n_slot,
1249                                                         EDMA_MAX_PARAMENTRY);
1250                 edma_info[j]->num_cc = min_t(unsigned, info[j].n_cc,
1251                                                         EDMA_MAX_CC);
1252
1253                 edma_info[j]->default_queue = info[j].default_queue;
1254                 if (!edma_info[j]->default_queue)
1255                         edma_info[j]->default_queue = EVENTQ_1;
1256
1257                 dev_dbg(&pdev->dev, "DMA REG BASE ADDR=%p\n",
1258                         edmacc_regs_base[j]);
1259
1260                 for (i = 0; i < edma_info[j]->num_slots; i++)
1261                         memcpy_toio(edmacc_regs_base[j] + PARM_OFFSET(i),
1262                                         &dummy_paramset, PARM_SIZE);
1263
1264                 noevent = info[j].noevent;
1265                 if (noevent) {
1266                         while (*noevent != -1)
1267                                 set_bit(*noevent++, edma_info[j]->edma_noevent);
1268                 }
1269
1270                 sprintf(irq_name, "edma%d", j);
1271                 irq[j] = platform_get_irq_byname(pdev, irq_name);
1272                 edma_info[j]->irq_res_start = irq[j];
1273                 status = request_irq(irq[j], dma_irq_handler, 0, "edma",
1274                                         &pdev->dev);
1275                 if (status < 0) {
1276                         dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1277                                 irq[j], status);
1278                         goto fail;
1279                 }
1280
1281                 sprintf(irq_name, "edma%d_err", j);
1282                 err_irq[j] = platform_get_irq_byname(pdev, irq_name);
1283                 edma_info[j]->irq_res_end = err_irq[j];
1284                 status = request_irq(err_irq[j], dma_ccerr_handler, 0,
1285                                         "edma_error", &pdev->dev);
1286                 if (status < 0) {
1287                         dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1288                                 err_irq[j], status);
1289                         goto fail;
1290                 }
1291
1292                 /* Everything lives on transfer controller 1 until otherwise
1293                  * specified. This way, long transfers on the low priority queue
1294                  * started by the codec engine will not cause audio defects.
1295                  */
1296                 for (i = 0; i < edma_info[j]->num_channels; i++)
1297                         map_dmach_queue(j, i, EVENTQ_1);
1298
1299                 queue_tc_mapping = info[j].queue_tc_mapping;
1300                 queue_priority_mapping = info[j].queue_priority_mapping;
1301
1302                 /* Event queue to TC mapping */
1303                 for (i = 0; queue_tc_mapping[i][0] != -1; i++)
1304                         map_queue_tc(j, queue_tc_mapping[i][0],
1305                                         queue_tc_mapping[i][1]);
1306
1307                 /* Event queue priority mapping */
1308                 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
1309                         assign_priority_to_queue(j,
1310                                                 queue_priority_mapping[i][0],
1311                                                 queue_priority_mapping[i][1]);
1312
1313                 /* Map the channel to param entry if channel mapping logic
1314                  * exist
1315                  */
1316                 if (edma_read(j, EDMA_CCCFG) & CHMAP_EXIST)
1317                         map_dmach_param(j);
1318
1319                 for (i = 0; i < info[j].n_region; i++) {
1320                         edma_write_array2(j, EDMA_DRAE, i, 0, 0x0);
1321                         edma_write_array2(j, EDMA_DRAE, i, 1, 0x0);
1322                         edma_write_array(j, EDMA_QRAE, i, 0x0);
1323                 }
1324         }
1325
1326         if (tc_errs_handled) {
1327                 status = request_irq(IRQ_TCERRINT0, dma_tc0err_handler, 0,
1328                                         "edma_tc0", &pdev->dev);
1329                 if (status < 0) {
1330                         dev_dbg(&pdev->dev, "request_irq %d failed --> %d\n",
1331                                 IRQ_TCERRINT0, status);
1332                         return status;
1333                 }
1334                 status = request_irq(IRQ_TCERRINT, dma_tc1err_handler, 0,
1335                                         "edma_tc1", &pdev->dev);
1336                 if (status < 0) {
1337                         dev_dbg(&pdev->dev, "request_irq %d --> %d\n",
1338                                 IRQ_TCERRINT, status);
1339                         return status;
1340                 }
1341         }
1342
1343         return 0;
1344
1345 fail:
1346         for (i = 0; i < EDMA_MAX_CC; i++) {
1347                 if (err_irq[i])
1348                         free_irq(err_irq[i], &pdev->dev);
1349                 if (irq[i])
1350                         free_irq(irq[i], &pdev->dev);
1351         }
1352 fail1:
1353         for (i = 0; i < EDMA_MAX_CC; i++) {
1354                 if (r[i])
1355                         release_mem_region(r[i]->start, len[i]);
1356                 if (edmacc_regs_base[i])
1357                         iounmap(edmacc_regs_base[i]);
1358                 kfree(edma_info[i]);
1359         }
1360         return status;
1361 }
1362
1363
1364 static struct platform_driver edma_driver = {
1365         .driver.name    = "edma",
1366 };
1367
1368 static int __init edma_init(void)
1369 {
1370         return platform_driver_probe(&edma_driver, edma_probe);
1371 }
1372 arch_initcall(edma_init);
1373