SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/gpio.h>
  17
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/dm646x.h>
  21 #include <mach/clock.h>
  22 #include <mach/cputype.h>
  23 #include <mach/edma.h>
  24 #include <mach/irqs.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/time.h>
  28 #include <mach/serial.h>
  29 #include <mach/common.h>
  30
  31 #include "clock.h"
  32 #include "mux.h"
  33
  34 /*
  35  * Device specific clocks
  36  */
  37 #define DM646X_REF_FREQ         27000000
  38 #define DM646X_AUX_FREQ         24000000
  39
  40 static struct pll_data pll1_data = {
  41         .num       = 1,
  42         .phys_base = DAVINCI_PLL1_BASE,
  43 };
  44
  45 static struct pll_data pll2_data = {
  46         .num       = 2,
  47         .phys_base = DAVINCI_PLL2_BASE,
  48 };
  49
  50 static struct clk ref_clk = {
  51         .name = "ref_clk",
  52         .rate = DM646X_REF_FREQ,
  53 };
  54
  55 static struct clk aux_clkin = {
  56         .name = "aux_clkin",
  57         .rate = DM646X_AUX_FREQ,
  58 };
  59
  60 static struct clk pll1_clk = {
  61         .name = "pll1",
  62         .parent = &ref_clk,
  63         .pll_data = &pll1_data,
  64         .flags = CLK_PLL,
  65 };
  66
  67 static struct clk pll1_sysclk1 = {
  68         .name = "pll1_sysclk1",
  69         .parent = &pll1_clk,
  70         .flags = CLK_PLL,
  71         .div_reg = PLLDIV1,
  72 };
  73
  74 static struct clk pll1_sysclk2 = {
  75         .name = "pll1_sysclk2",
  76         .parent = &pll1_clk,
  77         .flags = CLK_PLL,
  78         .div_reg = PLLDIV2,
  79 };
  80
  81 static struct clk pll1_sysclk3 = {
  82         .name = "pll1_sysclk3",
  83         .parent = &pll1_clk,
  84         .flags = CLK_PLL,
  85         .div_reg = PLLDIV3,
  86 };
  87
  88 static struct clk pll1_sysclk4 = {
  89         .name = "pll1_sysclk4",
  90         .parent = &pll1_clk,
  91         .flags = CLK_PLL,
  92         .div_reg = PLLDIV4,
  93 };
  94
  95 static struct clk pll1_sysclk5 = {
  96         .name = "pll1_sysclk5",
  97         .parent = &pll1_clk,
  98         .flags = CLK_PLL,
  99         .div_reg = PLLDIV5,
 100 };
 101
 102 static struct clk pll1_sysclk6 = {
 103         .name = "pll1_sysclk6",
 104         .parent = &pll1_clk,
 105         .flags = CLK_PLL,
 106         .div_reg = PLLDIV6,
 107 };
 108
 109 static struct clk pll1_sysclk8 = {
 110         .name = "pll1_sysclk8",
 111         .parent = &pll1_clk,
 112         .flags = CLK_PLL,
 113         .div_reg = PLLDIV8,
 114 };
 115
 116 static struct clk pll1_sysclk9 = {
 117         .name = "pll1_sysclk9",
 118         .parent = &pll1_clk,
 119         .flags = CLK_PLL,
 120         .div_reg = PLLDIV9,
 121 };
 122
 123 static struct clk pll1_sysclkbp = {
 124         .name = "pll1_sysclkbp",
 125         .parent = &pll1_clk,
 126         .flags = CLK_PLL | PRE_PLL,
 127         .div_reg = BPDIV,
 128 };
 129
 130 static struct clk pll1_aux_clk = {
 131         .name = "pll1_aux_clk",
 132         .parent = &pll1_clk,
 133         .flags = CLK_PLL | PRE_PLL,
 134 };
 135
 136 static struct clk pll2_clk = {
 137         .name = "pll2_clk",
 138         .parent = &ref_clk,
 139         .pll_data = &pll2_data,
 140         .flags = CLK_PLL,
 141 };
 142
 143 static struct clk pll2_sysclk1 = {
 144         .name = "pll2_sysclk1",
 145         .parent = &pll2_clk,
 146         .flags = CLK_PLL,
 147         .div_reg = PLLDIV1,
 148 };
 149
 150 static struct clk dsp_clk = {
 151         .name = "dsp",
 152         .parent = &pll1_sysclk1,
 153         .lpsc = DM646X_LPSC_C64X_CPU,
 154         .flags = PSC_DSP,
 155         .usecount = 1,                  /* REVISIT how to disable? */
 156 };
 157
 158 static struct clk arm_clk = {
 159         .name = "arm",
 160         .parent = &pll1_sysclk2,
 161         .lpsc = DM646X_LPSC_ARM,
 162         .flags = ALWAYS_ENABLED,
 163 };
 164
 165 static struct clk edma_cc_clk = {
 166         .name = "edma_cc",
 167         .parent = &pll1_sysclk2,
 168         .lpsc = DM646X_LPSC_TPCC,
 169         .flags = ALWAYS_ENABLED,
 170 };
 171
 172 static struct clk edma_tc0_clk = {
 173         .name = "edma_tc0",
 174         .parent = &pll1_sysclk2,
 175         .lpsc = DM646X_LPSC_TPTC0,
 176         .flags = ALWAYS_ENABLED,
 177 };
 178
 179 static struct clk edma_tc1_clk = {
 180         .name = "edma_tc1",
 181         .parent = &pll1_sysclk2,
 182         .lpsc = DM646X_LPSC_TPTC1,
 183         .flags = ALWAYS_ENABLED,
 184 };
 185
 186 static struct clk edma_tc2_clk = {
 187         .name = "edma_tc2",
 188         .parent = &pll1_sysclk2,
 189         .lpsc = DM646X_LPSC_TPTC2,
 190         .flags = ALWAYS_ENABLED,
 191 };
 192
 193 static struct clk edma_tc3_clk = {
 194         .name = "edma_tc3",
 195         .parent = &pll1_sysclk2,
 196         .lpsc = DM646X_LPSC_TPTC3,
 197         .flags = ALWAYS_ENABLED,
 198 };
 199
 200 static struct clk uart0_clk = {
 201         .name = "uart0",
 202         .parent = &aux_clkin,
 203         .lpsc = DM646X_LPSC_UART0,
 204 };
 205
 206 static struct clk uart1_clk = {
 207         .name = "uart1",
 208         .parent = &aux_clkin,
 209         .lpsc = DM646X_LPSC_UART1,
 210 };
 211
 212 static struct clk uart2_clk = {
 213         .name = "uart2",
 214         .parent = &aux_clkin,
 215         .lpsc = DM646X_LPSC_UART2,
 216 };
 217
 218 static struct clk i2c_clk = {
 219         .name = "I2CCLK",
 220         .parent = &pll1_sysclk3,
 221         .lpsc = DM646X_LPSC_I2C,
 222 };
 223
 224 static struct clk gpio_clk = {
 225         .name = "gpio",
 226         .parent = &pll1_sysclk3,
 227         .lpsc = DM646X_LPSC_GPIO,
 228 };
 229
 230 static struct clk mcasp0_clk = {
 231         .name = "mcasp0",
 232         .parent = &pll1_sysclk3,
 233         .lpsc = DM646X_LPSC_McASP0,
 234 };
 235
 236 static struct clk mcasp1_clk = {
 237         .name = "mcasp1",
 238         .parent = &pll1_sysclk3,
 239         .lpsc = DM646X_LPSC_McASP1,
 240 };
 241
 242 static struct clk aemif_clk = {
 243         .name = "aemif",
 244         .parent = &pll1_sysclk3,
 245         .lpsc = DM646X_LPSC_AEMIF,
 246         .flags = ALWAYS_ENABLED,
 247 };
 248
 249 static struct clk emac_clk = {
 250         .name = "emac",
 251         .parent = &pll1_sysclk3,
 252         .lpsc = DM646X_LPSC_EMAC,
 253 };
 254
 255 static struct clk pwm0_clk = {
 256         .name = "pwm0",
 257         .parent = &pll1_sysclk3,
 258         .lpsc = DM646X_LPSC_PWM0,
 259         .usecount = 1,            /* REVIST: disabling hangs system */
 260 };
 261
 262 static struct clk pwm1_clk = {
 263         .name = "pwm1",
 264         .parent = &pll1_sysclk3,
 265         .lpsc = DM646X_LPSC_PWM1,
 266         .usecount = 1,            /* REVIST: disabling hangs system */
 267 };
 268
 269 static struct clk timer0_clk = {
 270         .name = "timer0",
 271         .parent = &pll1_sysclk3,
 272         .lpsc = DM646X_LPSC_TIMER0,
 273 };
 274
 275 static struct clk timer1_clk = {
 276         .name = "timer1",
 277         .parent = &pll1_sysclk3,
 278         .lpsc = DM646X_LPSC_TIMER1,
 279 };
 280
 281 static struct clk timer2_clk = {
 282         .name = "timer2",
 283         .parent = &pll1_sysclk3,
 284         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 285 };
 286
 287 static struct clk vpif0_clk = {
 288         .name = "vpif0",
 289         .parent = &ref_clk,
 290         .lpsc = DM646X_LPSC_VPSSMSTR,
 291         .flags = ALWAYS_ENABLED,
 292 };
 293
 294 static struct clk vpif1_clk = {
 295         .name = "vpif1",
 296         .parent = &ref_clk,
 297         .lpsc = DM646X_LPSC_VPSSSLV,
 298         .flags = ALWAYS_ENABLED,
 299 };
 300
 301 struct davinci_clk dm646x_clks[] = {
 302         CLK(NULL, "ref", &ref_clk),
 303         CLK(NULL, "aux", &aux_clkin),
 304         CLK(NULL, "pll1", &pll1_clk),
 305         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 306         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 307         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 308         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 309         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 310         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 311         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 312         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 313         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 314         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 315         CLK(NULL, "pll2", &pll2_clk),
 316         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 317         CLK(NULL, "dsp", &dsp_clk),
 318         CLK(NULL, "arm", &arm_clk),
 319         CLK(NULL, "edma_cc", &edma_cc_clk),
 320         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 321         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 322         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 323         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 324         CLK(NULL, "uart0", &uart0_clk),
 325         CLK(NULL, "uart1", &uart1_clk),
 326         CLK(NULL, "uart2", &uart2_clk),
 327         CLK("i2c_davinci.1", NULL, &i2c_clk),
 328         CLK(NULL, "gpio", &gpio_clk),
 329         CLK(NULL, "mcasp0", &mcasp0_clk),
 330         CLK(NULL, "mcasp1", &mcasp1_clk),
 331         CLK(NULL, "aemif", &aemif_clk),
 332         CLK("davinci_emac.1", NULL, &emac_clk),
 333         CLK(NULL, "pwm0", &pwm0_clk),
 334         CLK(NULL, "pwm1", &pwm1_clk),
 335         CLK(NULL, "timer0", &timer0_clk),
 336         CLK(NULL, "timer1", &timer1_clk),
 337         CLK("watchdog", NULL, &timer2_clk),
 338         CLK(NULL, "vpif0", &vpif0_clk),
 339         CLK(NULL, "vpif1", &vpif1_clk),
 340         CLK(NULL, NULL, NULL),
 341 };
 342
 343 static struct emac_platform_data dm646x_emac_pdata = {
 344         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 345         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 346         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 347         .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
 348         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 349         .version                = EMAC_VERSION_2,
 350 };
 351
 352 static struct resource dm646x_emac_resources[] = {
 353         {
 354                 .start  = DM646X_EMAC_BASE,
 355                 .end    = DM646X_EMAC_BASE + 0x47ff,
 356                 .flags  = IORESOURCE_MEM,
 357         },
 358         {
 359                 .start  = IRQ_DM646X_EMACRXTHINT,
 360                 .end    = IRQ_DM646X_EMACRXTHINT,
 361                 .flags  = IORESOURCE_IRQ,
 362         },
 363         {
 364                 .start  = IRQ_DM646X_EMACRXINT,
 365                 .end    = IRQ_DM646X_EMACRXINT,
 366                 .flags  = IORESOURCE_IRQ,
 367         },
 368         {
 369                 .start  = IRQ_DM646X_EMACTXINT,
 370                 .end    = IRQ_DM646X_EMACTXINT,
 371                 .flags  = IORESOURCE_IRQ,
 372         },
 373         {
 374                 .start  = IRQ_DM646X_EMACMISCINT,
 375                 .end    = IRQ_DM646X_EMACMISCINT,
 376                 .flags  = IORESOURCE_IRQ,
 377         },
 378 };
 379
 380 static struct platform_device dm646x_emac_device = {
 381         .name           = "davinci_emac",
 382         .id             = 1,
 383         .dev = {
 384                 .platform_data  = &dm646x_emac_pdata,
 385         },
 386         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 387         .resource       = dm646x_emac_resources,
 388 };
 389
 390 #define PINMUX0         0x00
 391 #define PINMUX1         0x04
 392
 393 /*
 394  * Device specific mux setup
 395  *
 396  *      soc     description     mux  mode   mode  mux    dbg
 397  *                              reg  offset mask  mode
 398  */
 399 static const struct mux_config dm646x_pins[] = {
 400 #ifdef CONFIG_DAVINCI_MUX
 401 MUX_CFG(DM646X, ATAEN,          0,   0,     1,    1,     true)
 402
 403 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 404
 405 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 406
 407 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 408
 409 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 410
 411 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 412
 413 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 414
 415 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 416
 417 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 418
 419 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 420
 421 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 422
 423 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 424
 425 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 426
 427 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 428 #endif
 429 };
 430
 431 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 432         [IRQ_DM646X_VP_VERTINT0]        = 7,
 433         [IRQ_DM646X_VP_VERTINT1]        = 7,
 434         [IRQ_DM646X_VP_VERTINT2]        = 7,
 435         [IRQ_DM646X_VP_VERTINT3]        = 7,
 436         [IRQ_DM646X_VP_ERRINT]          = 7,
 437         [IRQ_DM646X_RESERVED_1]         = 7,
 438         [IRQ_DM646X_RESERVED_2]         = 7,
 439         [IRQ_DM646X_WDINT]              = 7,
 440         [IRQ_DM646X_CRGENINT0]          = 7,
 441         [IRQ_DM646X_CRGENINT1]          = 7,
 442         [IRQ_DM646X_TSIFINT0]           = 7,
 443         [IRQ_DM646X_TSIFINT1]           = 7,
 444         [IRQ_DM646X_VDCEINT]            = 7,
 445         [IRQ_DM646X_USBINT]             = 7,
 446         [IRQ_DM646X_USBDMAINT]          = 7,
 447         [IRQ_DM646X_PCIINT]             = 7,
 448         [IRQ_CCINT0]                    = 7,    /* dma */
 449         [IRQ_CCERRINT]                  = 7,    /* dma */
 450         [IRQ_TCERRINT0]                 = 7,    /* dma */
 451         [IRQ_TCERRINT]                  = 7,    /* dma */
 452         [IRQ_DM646X_TCERRINT2]          = 7,
 453         [IRQ_DM646X_TCERRINT3]          = 7,
 454         [IRQ_DM646X_IDE]                = 7,
 455         [IRQ_DM646X_HPIINT]             = 7,
 456         [IRQ_DM646X_EMACRXTHINT]        = 7,
 457         [IRQ_DM646X_EMACRXINT]          = 7,
 458         [IRQ_DM646X_EMACTXINT]          = 7,
 459         [IRQ_DM646X_EMACMISCINT]        = 7,
 460         [IRQ_DM646X_MCASP0TXINT]        = 7,
 461         [IRQ_DM646X_MCASP0RXINT]        = 7,
 462         [IRQ_AEMIFINT]                  = 7,
 463         [IRQ_DM646X_RESERVED_3]         = 7,
 464         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 465         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 466         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 467         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 468         [IRQ_PWMINT0]                   = 7,
 469         [IRQ_PWMINT1]                   = 7,
 470         [IRQ_DM646X_VLQINT]             = 7,
 471         [IRQ_I2C]                       = 7,
 472         [IRQ_UARTINT0]                  = 7,
 473         [IRQ_UARTINT1]                  = 7,
 474         [IRQ_DM646X_UARTINT2]           = 7,
 475         [IRQ_DM646X_SPINT0]             = 7,
 476         [IRQ_DM646X_SPINT1]             = 7,
 477         [IRQ_DM646X_DSP2ARMINT]         = 7,
 478         [IRQ_DM646X_RESERVED_4]         = 7,
 479         [IRQ_DM646X_PSCINT]             = 7,
 480         [IRQ_DM646X_GPIO0]              = 7,
 481         [IRQ_DM646X_GPIO1]              = 7,
 482         [IRQ_DM646X_GPIO2]              = 7,
 483         [IRQ_DM646X_GPIO3]              = 7,
 484         [IRQ_DM646X_GPIO4]              = 7,
 485         [IRQ_DM646X_GPIO5]              = 7,
 486         [IRQ_DM646X_GPIO6]              = 7,
 487         [IRQ_DM646X_GPIO7]              = 7,
 488         [IRQ_DM646X_GPIOBNK0]           = 7,
 489         [IRQ_DM646X_GPIOBNK1]           = 7,
 490         [IRQ_DM646X_GPIOBNK2]           = 7,
 491         [IRQ_DM646X_DDRINT]             = 7,
 492         [IRQ_DM646X_AEMIFINT]           = 7,
 493         [IRQ_COMMTX]                    = 7,
 494         [IRQ_COMMRX]                    = 7,
 495         [IRQ_EMUINT]                    = 7,
 496 };
 497
 498 /*----------------------------------------------------------------------*/
 499
 500 static const s8 dma_chan_dm646x_no_event[] = {
 501          0,  1,  2,  3, 13,
 502         14, 15, 24, 25, 26,
 503         27, 30, 31, 54, 55,
 504         56,
 505         -1
 506 };
 507
 508 /* Four Transfer Controllers on DM646x */
 509 static const s8
 510 dm646x_queue_tc_mapping[][2] = {
 511         /* {event queue no, TC no} */
 512         {0, 0},
 513         {1, 1},
 514         {2, 2},
 515         {3, 3},
 516         {-1, -1},
 517 };
 518
 519 static const s8
 520 dm646x_queue_priority_mapping[][2] = {
 521         /* {event queue no, Priority} */
 522         {0, 4},
 523         {1, 0},
 524         {2, 5},
 525         {3, 1},
 526         {-1, -1},
 527 };
 528
 529 static struct edma_soc_info dm646x_edma_info[] = {
 530         {
 531                 .n_channel              = 64,
 532                 .n_region               = 6,    /* 0-1, 4-7 */
 533                 .n_slot                 = 512,
 534                 .n_tc                   = 4,
 535                 .n_cc                   = 1,
 536                 .noevent                = dma_chan_dm646x_no_event,
 537                 .queue_tc_mapping       = dm646x_queue_tc_mapping,
 538                 .queue_priority_mapping = dm646x_queue_priority_mapping,
 539         },
 540 };
 541
 542 static struct resource edma_resources[] = {
 543         {
 544                 .name   = "edma_cc0",
 545                 .start  = 0x01c00000,
 546                 .end    = 0x01c00000 + SZ_64K - 1,
 547                 .flags  = IORESOURCE_MEM,
 548         },
 549         {
 550                 .name   = "edma_tc0",
 551                 .start  = 0x01c10000,
 552                 .end    = 0x01c10000 + SZ_1K - 1,
 553                 .flags  = IORESOURCE_MEM,
 554         },
 555         {
 556                 .name   = "edma_tc1",
 557                 .start  = 0x01c10400,
 558                 .end    = 0x01c10400 + SZ_1K - 1,
 559                 .flags  = IORESOURCE_MEM,
 560         },
 561         {
 562                 .name   = "edma_tc2",
 563                 .start  = 0x01c10800,
 564                 .end    = 0x01c10800 + SZ_1K - 1,
 565                 .flags  = IORESOURCE_MEM,
 566         },
 567         {
 568                 .name   = "edma_tc3",
 569                 .start  = 0x01c10c00,
 570                 .end    = 0x01c10c00 + SZ_1K - 1,
 571                 .flags  = IORESOURCE_MEM,
 572         },
 573         {
 574                 .name   = "edma0",
 575                 .start  = IRQ_CCINT0,
 576                 .flags  = IORESOURCE_IRQ,
 577         },
 578         {
 579                 .name   = "edma0_err",
 580                 .start  = IRQ_CCERRINT,
 581                 .flags  = IORESOURCE_IRQ,
 582         },
 583         /* not using TC*_ERR */
 584 };
 585
 586 static struct platform_device dm646x_edma_device = {
 587         .name                   = "edma",
 588         .id                     = 0,
 589         .dev.platform_data      = dm646x_edma_info,
 590         .num_resources          = ARRAY_SIZE(edma_resources),
 591         .resource               = edma_resources,
 592 };
 593
 594 /*----------------------------------------------------------------------*/
 595
 596 static struct map_desc dm646x_io_desc[] = {
 597         {
 598                 .virtual        = IO_VIRT,
 599                 .pfn            = __phys_to_pfn(IO_PHYS),
 600                 .length         = IO_SIZE,
 601                 .type           = MT_DEVICE
 602         },
 603         {
 604                 .virtual        = SRAM_VIRT,
 605                 .pfn            = __phys_to_pfn(0x00010000),
 606                 .length         = SZ_32K,
 607                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 608                 .type           = MT_DEVICE,
 609         },
 610 };
 611
 612 /* Contents of JTAG ID register used to identify exact cpu type */
 613 static struct davinci_id dm646x_ids[] = {
 614         {
 615                 .variant        = 0x0,
 616                 .part_no        = 0xb770,
 617                 .manufacturer   = 0x017,
 618                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 619                 .name           = "dm6467",
 620         },
 621 };
 622
 623 static void __iomem *dm646x_psc_bases[] = {
 624         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 625 };
 626
 627 /*
 628  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 629  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 630  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 631  * T1_TOP: Timer 1, top   :  <unused>
 632  */
 633 struct davinci_timer_info dm646x_timer_info = {
 634         .timers         = davinci_timer_instance,
 635         .clockevent_id  = T0_BOT,
 636         .clocksource_id = T0_TOP,
 637 };
 638
 639 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 640         {
 641                 .mapbase        = DAVINCI_UART0_BASE,
 642                 .irq            = IRQ_UARTINT0,
 643                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 644                                   UPF_IOREMAP,
 645                 .iotype         = UPIO_MEM32,
 646                 .regshift       = 2,
 647         },
 648         {
 649                 .mapbase        = DAVINCI_UART1_BASE,
 650                 .irq            = IRQ_UARTINT1,
 651                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 652                                   UPF_IOREMAP,
 653                 .iotype         = UPIO_MEM32,
 654                 .regshift       = 2,
 655         },
 656         {
 657                 .mapbase        = DAVINCI_UART2_BASE,
 658                 .irq            = IRQ_DM646X_UARTINT2,
 659                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 660                                   UPF_IOREMAP,
 661                 .iotype         = UPIO_MEM32,
 662                 .regshift       = 2,
 663         },
 664         {
 665                 .flags          = 0
 666         },
 667 };
 668
 669 static struct platform_device dm646x_serial_device = {
 670         .name                   = "serial8250",
 671         .id                     = PLAT8250_DEV_PLATFORM,
 672         .dev                    = {
 673                 .platform_data  = dm646x_serial_platform_data,
 674         },
 675 };
 676
 677 static struct davinci_soc_info davinci_soc_info_dm646x = {
 678         .io_desc                = dm646x_io_desc,
 679         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 680         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 681         .ids                    = dm646x_ids,
 682         .ids_num                = ARRAY_SIZE(dm646x_ids),
 683         .cpu_clks               = dm646x_clks,
 684         .psc_bases              = dm646x_psc_bases,
 685         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 686         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 687         .pinmux_pins            = dm646x_pins,
 688         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 689         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 690         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 691         .intc_irq_prios         = dm646x_default_priorities,
 692         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 693         .timer_info             = &dm646x_timer_info,
 694         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 695         .gpio_num               = 43, /* Only 33 usable */
 696         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 697         .serial_dev             = &dm646x_serial_device,
 698         .emac_pdata             = &dm646x_emac_pdata,
 699         .sram_dma               = 0x10010000,
 700         .sram_len               = SZ_32K,
 701 };
 702
 703 void __init dm646x_init(void)
 704 {
 705         davinci_common_init(&davinci_soc_info_dm646x);
 706 }
 707
 708 static int __init dm646x_init_devices(void)
 709 {
 710         if (!cpu_is_davinci_dm646x())
 711                 return 0;
 712
 713         platform_device_register(&dm646x_edma_device);
 714         platform_device_register(&dm646x_emac_device);
 715         return 0;
 716 }
 717 postcore_initcall(dm646x_init_devices);