2 * TI DaVinci DM644x chip specific setup
4 * Author: Kevin Hilman, Deep Root Systems, LLC
6 * 2007 (c) Deep Root Systems, LLC. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/init.h>
13 #include <linux/clk.h>
14 #include <linux/platform_device.h>
16 #include <asm/mach/map.h>
18 #include <mach/dm646x.h>
19 #include <mach/clock.h>
20 #include <mach/cputype.h>
21 #include <mach/edma.h>
22 #include <mach/irqs.h>
25 #include <mach/common.h>
31 * Device specific clocks
33 #define DM646X_REF_FREQ 27000000
34 #define DM646X_AUX_FREQ 24000000
36 static struct pll_data pll1_data = {
38 .phys_base = DAVINCI_PLL1_BASE,
41 static struct pll_data pll2_data = {
43 .phys_base = DAVINCI_PLL2_BASE,
46 static struct clk ref_clk = {
48 .rate = DM646X_REF_FREQ,
51 static struct clk aux_clkin = {
53 .rate = DM646X_AUX_FREQ,
56 static struct clk pll1_clk = {
59 .pll_data = &pll1_data,
63 static struct clk pll1_sysclk1 = {
64 .name = "pll1_sysclk1",
70 static struct clk pll1_sysclk2 = {
71 .name = "pll1_sysclk2",
77 static struct clk pll1_sysclk3 = {
78 .name = "pll1_sysclk3",
84 static struct clk pll1_sysclk4 = {
85 .name = "pll1_sysclk4",
91 static struct clk pll1_sysclk5 = {
92 .name = "pll1_sysclk5",
98 static struct clk pll1_sysclk6 = {
99 .name = "pll1_sysclk6",
105 static struct clk pll1_sysclk8 = {
106 .name = "pll1_sysclk8",
112 static struct clk pll1_sysclk9 = {
113 .name = "pll1_sysclk9",
119 static struct clk pll1_sysclkbp = {
120 .name = "pll1_sysclkbp",
122 .flags = CLK_PLL | PRE_PLL,
126 static struct clk pll1_aux_clk = {
127 .name = "pll1_aux_clk",
129 .flags = CLK_PLL | PRE_PLL,
132 static struct clk pll2_clk = {
135 .pll_data = &pll2_data,
139 static struct clk pll2_sysclk1 = {
140 .name = "pll2_sysclk1",
146 static struct clk dsp_clk = {
148 .parent = &pll1_sysclk1,
149 .lpsc = DM646X_LPSC_C64X_CPU,
151 .usecount = 1, /* REVISIT how to disable? */
154 static struct clk arm_clk = {
156 .parent = &pll1_sysclk2,
157 .lpsc = DM646X_LPSC_ARM,
158 .flags = ALWAYS_ENABLED,
161 static struct clk uart0_clk = {
163 .parent = &aux_clkin,
164 .lpsc = DM646X_LPSC_UART0,
167 static struct clk uart1_clk = {
169 .parent = &aux_clkin,
170 .lpsc = DM646X_LPSC_UART1,
173 static struct clk uart2_clk = {
175 .parent = &aux_clkin,
176 .lpsc = DM646X_LPSC_UART2,
179 static struct clk i2c_clk = {
181 .parent = &pll1_sysclk3,
182 .lpsc = DM646X_LPSC_I2C,
185 static struct clk gpio_clk = {
187 .parent = &pll1_sysclk3,
188 .lpsc = DM646X_LPSC_GPIO,
191 static struct clk aemif_clk = {
193 .parent = &pll1_sysclk3,
194 .lpsc = DM646X_LPSC_AEMIF,
195 .flags = ALWAYS_ENABLED,
198 static struct clk emac_clk = {
200 .parent = &pll1_sysclk3,
201 .lpsc = DM646X_LPSC_EMAC,
204 static struct clk pwm0_clk = {
206 .parent = &pll1_sysclk3,
207 .lpsc = DM646X_LPSC_PWM0,
208 .usecount = 1, /* REVIST: disabling hangs system */
211 static struct clk pwm1_clk = {
213 .parent = &pll1_sysclk3,
214 .lpsc = DM646X_LPSC_PWM1,
215 .usecount = 1, /* REVIST: disabling hangs system */
218 static struct clk timer0_clk = {
220 .parent = &pll1_sysclk3,
221 .lpsc = DM646X_LPSC_TIMER0,
224 static struct clk timer1_clk = {
226 .parent = &pll1_sysclk3,
227 .lpsc = DM646X_LPSC_TIMER1,
230 static struct clk timer2_clk = {
232 .parent = &pll1_sysclk3,
233 .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
236 static struct clk vpif0_clk = {
239 .lpsc = DM646X_LPSC_VPSSMSTR,
240 .flags = ALWAYS_ENABLED,
243 static struct clk vpif1_clk = {
246 .lpsc = DM646X_LPSC_VPSSSLV,
247 .flags = ALWAYS_ENABLED,
250 struct davinci_clk dm646x_clks[] = {
251 CLK(NULL, "ref", &ref_clk),
252 CLK(NULL, "aux", &aux_clkin),
253 CLK(NULL, "pll1", &pll1_clk),
254 CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
255 CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
256 CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
257 CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
258 CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
259 CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
260 CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
261 CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
262 CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
263 CLK(NULL, "pll1_aux", &pll1_aux_clk),
264 CLK(NULL, "pll2", &pll2_clk),
265 CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
266 CLK(NULL, "dsp", &dsp_clk),
267 CLK(NULL, "arm", &arm_clk),
268 CLK(NULL, "uart0", &uart0_clk),
269 CLK(NULL, "uart1", &uart1_clk),
270 CLK(NULL, "uart2", &uart2_clk),
271 CLK("i2c_davinci.1", NULL, &i2c_clk),
272 CLK(NULL, "gpio", &gpio_clk),
273 CLK(NULL, "aemif", &aemif_clk),
274 CLK("davinci_emac.1", NULL, &emac_clk),
275 CLK(NULL, "pwm0", &pwm0_clk),
276 CLK(NULL, "pwm1", &pwm1_clk),
277 CLK(NULL, "timer0", &timer0_clk),
278 CLK(NULL, "timer1", &timer1_clk),
279 CLK("watchdog", NULL, &timer2_clk),
280 CLK(NULL, "vpif0", &vpif0_clk),
281 CLK(NULL, "vpif1", &vpif1_clk),
282 CLK(NULL, NULL, NULL),
285 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
286 static struct resource dm646x_emac_resources[] = {
288 .start = DM646X_EMAC_BASE,
289 .end = DM646X_EMAC_BASE + 0x47ff,
290 .flags = IORESOURCE_MEM,
293 .start = IRQ_DM646X_EMACRXTHINT,
294 .end = IRQ_DM646X_EMACRXTHINT,
295 .flags = IORESOURCE_IRQ,
298 .start = IRQ_DM646X_EMACRXINT,
299 .end = IRQ_DM646X_EMACRXINT,
300 .flags = IORESOURCE_IRQ,
303 .start = IRQ_DM646X_EMACTXINT,
304 .end = IRQ_DM646X_EMACTXINT,
305 .flags = IORESOURCE_IRQ,
308 .start = IRQ_DM646X_EMACMISCINT,
309 .end = IRQ_DM646X_EMACMISCINT,
310 .flags = IORESOURCE_IRQ,
314 static struct platform_device dm646x_emac_device = {
315 .name = "davinci_emac",
317 .num_resources = ARRAY_SIZE(dm646x_emac_resources),
318 .resource = dm646x_emac_resources,
324 * Device specific mux setup
326 * soc description mux mode mode mux dbg
327 * reg offset mask mode
329 static const struct mux_config dm646x_pins[] = {
330 #ifdef CONFIG_DAVINCI_MUX
331 MUX_CFG(DM646X, ATAEN, 0, 0, 1, 1, true)
333 MUX_CFG(DM646X, AUDCK1, 0, 29, 1, 0, false)
335 MUX_CFG(DM646X, AUDCK0, 0, 28, 1, 0, false)
337 MUX_CFG(DM646X, CRGMUX, 0, 24, 7, 5, true)
339 MUX_CFG(DM646X, STSOMUX_DISABLE, 0, 22, 3, 0, true)
341 MUX_CFG(DM646X, STSIMUX_DISABLE, 0, 20, 3, 0, true)
343 MUX_CFG(DM646X, PTSOMUX_DISABLE, 0, 18, 3, 0, true)
345 MUX_CFG(DM646X, PTSIMUX_DISABLE, 0, 16, 3, 0, true)
347 MUX_CFG(DM646X, STSOMUX, 0, 22, 3, 2, true)
349 MUX_CFG(DM646X, STSIMUX, 0, 20, 3, 2, true)
351 MUX_CFG(DM646X, PTSOMUX_PARALLEL, 0, 18, 3, 2, true)
353 MUX_CFG(DM646X, PTSIMUX_PARALLEL, 0, 16, 3, 2, true)
355 MUX_CFG(DM646X, PTSOMUX_SERIAL, 0, 18, 3, 3, true)
357 MUX_CFG(DM646X, PTSIMUX_SERIAL, 0, 16, 3, 3, true)
361 /*----------------------------------------------------------------------*/
363 static const s8 dma_chan_dm646x_no_event[] = {
371 static struct edma_soc_info dm646x_edma_info = {
373 .n_region = 6, /* 0-1, 4-7 */
376 .noevent = dma_chan_dm646x_no_event,
379 static struct resource edma_resources[] = {
383 .end = 0x01c00000 + SZ_64K - 1,
384 .flags = IORESOURCE_MEM,
389 .end = 0x01c10000 + SZ_1K - 1,
390 .flags = IORESOURCE_MEM,
395 .end = 0x01c10400 + SZ_1K - 1,
396 .flags = IORESOURCE_MEM,
401 .end = 0x01c10800 + SZ_1K - 1,
402 .flags = IORESOURCE_MEM,
407 .end = 0x01c10c00 + SZ_1K - 1,
408 .flags = IORESOURCE_MEM,
412 .flags = IORESOURCE_IRQ,
415 .start = IRQ_CCERRINT,
416 .flags = IORESOURCE_IRQ,
418 /* not using TC*_ERR */
421 static struct platform_device dm646x_edma_device = {
424 .dev.platform_data = &dm646x_edma_info,
425 .num_resources = ARRAY_SIZE(edma_resources),
426 .resource = edma_resources,
429 /*----------------------------------------------------------------------*/
431 #if defined(CONFIG_TI_DAVINCI_EMAC) || defined(CONFIG_TI_DAVINCI_EMAC_MODULE)
433 void dm646x_init_emac(struct emac_platform_data *pdata)
435 pdata->ctrl_reg_offset = DM646X_EMAC_CNTRL_OFFSET;
436 pdata->ctrl_mod_reg_offset = DM646X_EMAC_CNTRL_MOD_OFFSET;
437 pdata->ctrl_ram_offset = DM646X_EMAC_CNTRL_RAM_OFFSET;
438 pdata->mdio_reg_offset = DM646X_EMAC_MDIO_OFFSET;
439 pdata->ctrl_ram_size = DM646X_EMAC_CNTRL_RAM_SIZE;
440 pdata->version = EMAC_VERSION_2;
441 dm646x_emac_device.dev.platform_data = pdata;
442 platform_device_register(&dm646x_emac_device);
446 void dm646x_init_emac(struct emac_platform_data *unused) {}
450 static struct map_desc dm646x_io_desc[] = {
453 .pfn = __phys_to_pfn(IO_PHYS),
459 /* Contents of JTAG ID register used to identify exact cpu type */
460 static struct davinci_id dm646x_ids[] = {
464 .manufacturer = 0x017,
465 .cpu_id = DAVINCI_CPU_ID_DM6467,
470 static void __iomem *dm646x_psc_bases[] = {
471 IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
474 static struct davinci_soc_info davinci_soc_info_dm646x = {
475 .io_desc = dm646x_io_desc,
476 .io_desc_num = ARRAY_SIZE(dm646x_io_desc),
477 .jtag_id_base = IO_ADDRESS(0x01c40028),
479 .ids_num = ARRAY_SIZE(dm646x_ids),
480 .cpu_clks = dm646x_clks,
481 .psc_bases = dm646x_psc_bases,
482 .psc_bases_num = ARRAY_SIZE(dm646x_psc_bases),
483 .pinmux_base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
484 .pinmux_pins = dm646x_pins,
485 .pinmux_pins_num = ARRAY_SIZE(dm646x_pins),
488 void __init dm646x_init(void)
490 davinci_common_init(&davinci_soc_info_dm646x);
493 static int __init dm646x_init_devices(void)
495 if (!cpu_is_davinci_dm646x())
498 platform_device_register(&dm646x_edma_device);
501 postcore_initcall(dm646x_init_devices);