SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/init.h>
  12 #include <linux/clk.h>
  13 #include <linux/serial_8250.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/gpio.h>
  16
  17 #include <asm/mach/map.h>
  18
  19 #include <mach/dm646x.h>
  20 #include <mach/cputype.h>
  21 #include <mach/edma.h>
  22 #include <mach/irqs.h>
  23 #include <mach/psc.h>
  24 #include <mach/mux.h>
  25 #include <mach/time.h>
  26 #include <mach/serial.h>
  27 #include <mach/common.h>
  28 #include <mach/asp.h>
  29
  30 #include "clock.h"
  31 #include "mux.h"
  32
  33 #define DAVINCI_VPIF_BASE       (0x01C12000)
  34 #define VDD3P3V_PWDN_OFFSET     (0x48)
  35 #define VSCLKDIS_OFFSET         (0x6C)
  36
  37 #define VDD3P3V_VID_MASK        (BIT_MASK(3) | BIT_MASK(2) | BIT_MASK(1) |\
  38                                         BIT_MASK(0))
  39 #define VSCLKDIS_MASK           (BIT_MASK(11) | BIT_MASK(10) | BIT_MASK(9) |\
  40                                         BIT_MASK(8))
  41
  42 /*
  43  * Device specific clocks
  44  */
  45 #define DM646X_AUX_FREQ         24000000
  46
  47 static struct pll_data pll1_data = {
  48         .num       = 1,
  49         .phys_base = DAVINCI_PLL1_BASE,
  50 };
  51
  52 static struct pll_data pll2_data = {
  53         .num       = 2,
  54         .phys_base = DAVINCI_PLL2_BASE,
  55 };
  56
  57 static struct clk ref_clk = {
  58         .name = "ref_clk",
  59 };
  60
  61 static struct clk aux_clkin = {
  62         .name = "aux_clkin",
  63         .rate = DM646X_AUX_FREQ,
  64 };
  65
  66 static struct clk pll1_clk = {
  67         .name = "pll1",
  68         .parent = &ref_clk,
  69         .pll_data = &pll1_data,
  70         .flags = CLK_PLL,
  71 };
  72
  73 static struct clk pll1_sysclk1 = {
  74         .name = "pll1_sysclk1",
  75         .parent = &pll1_clk,
  76         .flags = CLK_PLL,
  77         .div_reg = PLLDIV1,
  78 };
  79
  80 static struct clk pll1_sysclk2 = {
  81         .name = "pll1_sysclk2",
  82         .parent = &pll1_clk,
  83         .flags = CLK_PLL,
  84         .div_reg = PLLDIV2,
  85 };
  86
  87 static struct clk pll1_sysclk3 = {
  88         .name = "pll1_sysclk3",
  89         .parent = &pll1_clk,
  90         .flags = CLK_PLL,
  91         .div_reg = PLLDIV3,
  92 };
  93
  94 static struct clk pll1_sysclk4 = {
  95         .name = "pll1_sysclk4",
  96         .parent = &pll1_clk,
  97         .flags = CLK_PLL,
  98         .div_reg = PLLDIV4,
  99 };
 100
 101 static struct clk pll1_sysclk5 = {
 102         .name = "pll1_sysclk5",
 103         .parent = &pll1_clk,
 104         .flags = CLK_PLL,
 105         .div_reg = PLLDIV5,
 106 };
 107
 108 static struct clk pll1_sysclk6 = {
 109         .name = "pll1_sysclk6",
 110         .parent = &pll1_clk,
 111         .flags = CLK_PLL,
 112         .div_reg = PLLDIV6,
 113 };
 114
 115 static struct clk pll1_sysclk8 = {
 116         .name = "pll1_sysclk8",
 117         .parent = &pll1_clk,
 118         .flags = CLK_PLL,
 119         .div_reg = PLLDIV8,
 120 };
 121
 122 static struct clk pll1_sysclk9 = {
 123         .name = "pll1_sysclk9",
 124         .parent = &pll1_clk,
 125         .flags = CLK_PLL,
 126         .div_reg = PLLDIV9,
 127 };
 128
 129 static struct clk pll1_sysclkbp = {
 130         .name = "pll1_sysclkbp",
 131         .parent = &pll1_clk,
 132         .flags = CLK_PLL | PRE_PLL,
 133         .div_reg = BPDIV,
 134 };
 135
 136 static struct clk pll1_aux_clk = {
 137         .name = "pll1_aux_clk",
 138         .parent = &pll1_clk,
 139         .flags = CLK_PLL | PRE_PLL,
 140 };
 141
 142 static struct clk pll2_clk = {
 143         .name = "pll2_clk",
 144         .parent = &ref_clk,
 145         .pll_data = &pll2_data,
 146         .flags = CLK_PLL,
 147 };
 148
 149 static struct clk pll2_sysclk1 = {
 150         .name = "pll2_sysclk1",
 151         .parent = &pll2_clk,
 152         .flags = CLK_PLL,
 153         .div_reg = PLLDIV1,
 154 };
 155
 156 static struct clk dsp_clk = {
 157         .name = "dsp",
 158         .parent = &pll1_sysclk1,
 159         .lpsc = DM646X_LPSC_C64X_CPU,
 160         .flags = PSC_DSP,
 161         .usecount = 1,                  /* REVISIT how to disable? */
 162 };
 163
 164 static struct clk arm_clk = {
 165         .name = "arm",
 166         .parent = &pll1_sysclk2,
 167         .lpsc = DM646X_LPSC_ARM,
 168         .flags = ALWAYS_ENABLED,
 169 };
 170
 171 static struct clk edma_cc_clk = {
 172         .name = "edma_cc",
 173         .parent = &pll1_sysclk2,
 174         .lpsc = DM646X_LPSC_TPCC,
 175         .flags = ALWAYS_ENABLED,
 176 };
 177
 178 static struct clk edma_tc0_clk = {
 179         .name = "edma_tc0",
 180         .parent = &pll1_sysclk2,
 181         .lpsc = DM646X_LPSC_TPTC0,
 182         .flags = ALWAYS_ENABLED,
 183 };
 184
 185 static struct clk edma_tc1_clk = {
 186         .name = "edma_tc1",
 187         .parent = &pll1_sysclk2,
 188         .lpsc = DM646X_LPSC_TPTC1,
 189         .flags = ALWAYS_ENABLED,
 190 };
 191
 192 static struct clk edma_tc2_clk = {
 193         .name = "edma_tc2",
 194         .parent = &pll1_sysclk2,
 195         .lpsc = DM646X_LPSC_TPTC2,
 196         .flags = ALWAYS_ENABLED,
 197 };
 198
 199 static struct clk edma_tc3_clk = {
 200         .name = "edma_tc3",
 201         .parent = &pll1_sysclk2,
 202         .lpsc = DM646X_LPSC_TPTC3,
 203         .flags = ALWAYS_ENABLED,
 204 };
 205
 206 static struct clk uart0_clk = {
 207         .name = "uart0",
 208         .parent = &aux_clkin,
 209         .lpsc = DM646X_LPSC_UART0,
 210 };
 211
 212 static struct clk uart1_clk = {
 213         .name = "uart1",
 214         .parent = &aux_clkin,
 215         .lpsc = DM646X_LPSC_UART1,
 216 };
 217
 218 static struct clk uart2_clk = {
 219         .name = "uart2",
 220         .parent = &aux_clkin,
 221         .lpsc = DM646X_LPSC_UART2,
 222 };
 223
 224 static struct clk i2c_clk = {
 225         .name = "I2CCLK",
 226         .parent = &pll1_sysclk3,
 227         .lpsc = DM646X_LPSC_I2C,
 228 };
 229
 230 static struct clk gpio_clk = {
 231         .name = "gpio",
 232         .parent = &pll1_sysclk3,
 233         .lpsc = DM646X_LPSC_GPIO,
 234 };
 235
 236 static struct clk mcasp0_clk = {
 237         .name = "mcasp0",
 238         .parent = &pll1_sysclk3,
 239         .lpsc = DM646X_LPSC_McASP0,
 240 };
 241
 242 static struct clk mcasp1_clk = {
 243         .name = "mcasp1",
 244         .parent = &pll1_sysclk3,
 245         .lpsc = DM646X_LPSC_McASP1,
 246 };
 247
 248 static struct clk aemif_clk = {
 249         .name = "aemif",
 250         .parent = &pll1_sysclk3,
 251         .lpsc = DM646X_LPSC_AEMIF,
 252         .flags = ALWAYS_ENABLED,
 253 };
 254
 255 static struct clk emac_clk = {
 256         .name = "emac",
 257         .parent = &pll1_sysclk3,
 258         .lpsc = DM646X_LPSC_EMAC,
 259 };
 260
 261 static struct clk pwm0_clk = {
 262         .name = "pwm0",
 263         .parent = &pll1_sysclk3,
 264         .lpsc = DM646X_LPSC_PWM0,
 265         .usecount = 1,            /* REVIST: disabling hangs system */
 266 };
 267
 268 static struct clk pwm1_clk = {
 269         .name = "pwm1",
 270         .parent = &pll1_sysclk3,
 271         .lpsc = DM646X_LPSC_PWM1,
 272         .usecount = 1,            /* REVIST: disabling hangs system */
 273 };
 274
 275 static struct clk timer0_clk = {
 276         .name = "timer0",
 277         .parent = &pll1_sysclk3,
 278         .lpsc = DM646X_LPSC_TIMER0,
 279 };
 280
 281 static struct clk timer1_clk = {
 282         .name = "timer1",
 283         .parent = &pll1_sysclk3,
 284         .lpsc = DM646X_LPSC_TIMER1,
 285 };
 286
 287 static struct clk timer2_clk = {
 288         .name = "timer2",
 289         .parent = &pll1_sysclk3,
 290         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 291 };
 292
 293
 294 static struct clk ide_clk = {
 295         .name = "ide",
 296         .parent = &pll1_sysclk4,
 297         .lpsc = DAVINCI_LPSC_ATA,
 298 };
 299
 300 static struct clk vpif0_clk = {
 301         .name = "vpif0",
 302         .parent = &ref_clk,
 303         .lpsc = DM646X_LPSC_VPSSMSTR,
 304         .flags = ALWAYS_ENABLED,
 305 };
 306
 307 static struct clk vpif1_clk = {
 308         .name = "vpif1",
 309         .parent = &ref_clk,
 310         .lpsc = DM646X_LPSC_VPSSSLV,
 311         .flags = ALWAYS_ENABLED,
 312 };
 313
 314 struct davinci_clk dm646x_clks[] = {
 315         CLK(NULL, "ref", &ref_clk),
 316         CLK(NULL, "aux", &aux_clkin),
 317         CLK(NULL, "pll1", &pll1_clk),
 318         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 319         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 320         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 321         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 322         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 323         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 324         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 325         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 326         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 327         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 328         CLK(NULL, "pll2", &pll2_clk),
 329         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 330         CLK(NULL, "dsp", &dsp_clk),
 331         CLK(NULL, "arm", &arm_clk),
 332         CLK(NULL, "edma_cc", &edma_cc_clk),
 333         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 334         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 335         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 336         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 337         CLK(NULL, "uart0", &uart0_clk),
 338         CLK(NULL, "uart1", &uart1_clk),
 339         CLK(NULL, "uart2", &uart2_clk),
 340         CLK("i2c_davinci.1", NULL, &i2c_clk),
 341         CLK(NULL, "gpio", &gpio_clk),
 342         CLK("davinci-mcasp.0", NULL, &mcasp0_clk),
 343         CLK("davinci-mcasp.1", NULL, &mcasp1_clk),
 344         CLK(NULL, "aemif", &aemif_clk),
 345         CLK("davinci_emac.1", NULL, &emac_clk),
 346         CLK(NULL, "pwm0", &pwm0_clk),
 347         CLK(NULL, "pwm1", &pwm1_clk),
 348         CLK(NULL, "timer0", &timer0_clk),
 349         CLK(NULL, "timer1", &timer1_clk),
 350         CLK("watchdog", NULL, &timer2_clk),
 351         CLK("palm_bk3710", NULL, &ide_clk),
 352         CLK(NULL, "vpif0", &vpif0_clk),
 353         CLK(NULL, "vpif1", &vpif1_clk),
 354         CLK(NULL, NULL, NULL),
 355 };
 356
 357 static struct emac_platform_data dm646x_emac_pdata = {
 358         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 359         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 360         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 361         .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
 362         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 363         .version                = EMAC_VERSION_2,
 364 };
 365
 366 static struct resource dm646x_emac_resources[] = {
 367         {
 368                 .start  = DM646X_EMAC_BASE,
 369                 .end    = DM646X_EMAC_BASE + 0x47ff,
 370                 .flags  = IORESOURCE_MEM,
 371         },
 372         {
 373                 .start  = IRQ_DM646X_EMACRXTHINT,
 374                 .end    = IRQ_DM646X_EMACRXTHINT,
 375                 .flags  = IORESOURCE_IRQ,
 376         },
 377         {
 378                 .start  = IRQ_DM646X_EMACRXINT,
 379                 .end    = IRQ_DM646X_EMACRXINT,
 380                 .flags  = IORESOURCE_IRQ,
 381         },
 382         {
 383                 .start  = IRQ_DM646X_EMACTXINT,
 384                 .end    = IRQ_DM646X_EMACTXINT,
 385                 .flags  = IORESOURCE_IRQ,
 386         },
 387         {
 388                 .start  = IRQ_DM646X_EMACMISCINT,
 389                 .end    = IRQ_DM646X_EMACMISCINT,
 390                 .flags  = IORESOURCE_IRQ,
 391         },
 392 };
 393
 394 static struct platform_device dm646x_emac_device = {
 395         .name           = "davinci_emac",
 396         .id             = 1,
 397         .dev = {
 398                 .platform_data  = &dm646x_emac_pdata,
 399         },
 400         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 401         .resource       = dm646x_emac_resources,
 402 };
 403
 404 #define PINMUX0         0x00
 405 #define PINMUX1         0x04
 406
 407 /*
 408  * Device specific mux setup
 409  *
 410  *      soc     description     mux  mode   mode  mux    dbg
 411  *                              reg  offset mask  mode
 412  */
 413 static const struct mux_config dm646x_pins[] = {
 414 #ifdef CONFIG_DAVINCI_MUX
 415 MUX_CFG(DM646X, ATAEN,          0,   0,     5,    1,     true)
 416
 417 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 418
 419 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 420
 421 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 422
 423 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 424
 425 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 426
 427 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 428
 429 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 430
 431 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 432
 433 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 434
 435 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 436
 437 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 438
 439 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 440
 441 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 442 #endif
 443 };
 444
 445 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 446         [IRQ_DM646X_VP_VERTINT0]        = 7,
 447         [IRQ_DM646X_VP_VERTINT1]        = 7,
 448         [IRQ_DM646X_VP_VERTINT2]        = 7,
 449         [IRQ_DM646X_VP_VERTINT3]        = 7,
 450         [IRQ_DM646X_VP_ERRINT]          = 7,
 451         [IRQ_DM646X_RESERVED_1]         = 7,
 452         [IRQ_DM646X_RESERVED_2]         = 7,
 453         [IRQ_DM646X_WDINT]              = 7,
 454         [IRQ_DM646X_CRGENINT0]          = 7,
 455         [IRQ_DM646X_CRGENINT1]          = 7,
 456         [IRQ_DM646X_TSIFINT0]           = 7,
 457         [IRQ_DM646X_TSIFINT1]           = 7,
 458         [IRQ_DM646X_VDCEINT]            = 7,
 459         [IRQ_DM646X_USBINT]             = 7,
 460         [IRQ_DM646X_USBDMAINT]          = 7,
 461         [IRQ_DM646X_PCIINT]             = 7,
 462         [IRQ_CCINT0]                    = 7,    /* dma */
 463         [IRQ_CCERRINT]                  = 7,    /* dma */
 464         [IRQ_TCERRINT0]                 = 7,    /* dma */
 465         [IRQ_TCERRINT]                  = 7,    /* dma */
 466         [IRQ_DM646X_TCERRINT2]          = 7,
 467         [IRQ_DM646X_TCERRINT3]          = 7,
 468         [IRQ_DM646X_IDE]                = 7,
 469         [IRQ_DM646X_HPIINT]             = 7,
 470         [IRQ_DM646X_EMACRXTHINT]        = 7,
 471         [IRQ_DM646X_EMACRXINT]          = 7,
 472         [IRQ_DM646X_EMACTXINT]          = 7,
 473         [IRQ_DM646X_EMACMISCINT]        = 7,
 474         [IRQ_DM646X_MCASP0TXINT]        = 7,
 475         [IRQ_DM646X_MCASP0RXINT]        = 7,
 476         [IRQ_AEMIFINT]                  = 7,
 477         [IRQ_DM646X_RESERVED_3]         = 7,
 478         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 479         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 480         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 481         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 482         [IRQ_PWMINT0]                   = 7,
 483         [IRQ_PWMINT1]                   = 7,
 484         [IRQ_DM646X_VLQINT]             = 7,
 485         [IRQ_I2C]                       = 7,
 486         [IRQ_UARTINT0]                  = 7,
 487         [IRQ_UARTINT1]                  = 7,
 488         [IRQ_DM646X_UARTINT2]           = 7,
 489         [IRQ_DM646X_SPINT0]             = 7,
 490         [IRQ_DM646X_SPINT1]             = 7,
 491         [IRQ_DM646X_DSP2ARMINT]         = 7,
 492         [IRQ_DM646X_RESERVED_4]         = 7,
 493         [IRQ_DM646X_PSCINT]             = 7,
 494         [IRQ_DM646X_GPIO0]              = 7,
 495         [IRQ_DM646X_GPIO1]              = 7,
 496         [IRQ_DM646X_GPIO2]              = 7,
 497         [IRQ_DM646X_GPIO3]              = 7,
 498         [IRQ_DM646X_GPIO4]              = 7,
 499         [IRQ_DM646X_GPIO5]              = 7,
 500         [IRQ_DM646X_GPIO6]              = 7,
 501         [IRQ_DM646X_GPIO7]              = 7,
 502         [IRQ_DM646X_GPIOBNK0]           = 7,
 503         [IRQ_DM646X_GPIOBNK1]           = 7,
 504         [IRQ_DM646X_GPIOBNK2]           = 7,
 505         [IRQ_DM646X_DDRINT]             = 7,
 506         [IRQ_DM646X_AEMIFINT]           = 7,
 507         [IRQ_COMMTX]                    = 7,
 508         [IRQ_COMMRX]                    = 7,
 509         [IRQ_EMUINT]                    = 7,
 510 };
 511
 512 /*----------------------------------------------------------------------*/
 513
 514 static const s8 dma_chan_dm646x_no_event[] = {
 515          0,  1,  2,  3, 13,
 516         14, 15, 24, 25, 26,
 517         27, 30, 31, 54, 55,
 518         56,
 519         -1
 520 };
 521
 522 /* Four Transfer Controllers on DM646x */
 523 static const s8
 524 dm646x_queue_tc_mapping[][2] = {
 525         /* {event queue no, TC no} */
 526         {0, 0},
 527         {1, 1},
 528         {2, 2},
 529         {3, 3},
 530         {-1, -1},
 531 };
 532
 533 static const s8
 534 dm646x_queue_priority_mapping[][2] = {
 535         /* {event queue no, Priority} */
 536         {0, 4},
 537         {1, 0},
 538         {2, 5},
 539         {3, 1},
 540         {-1, -1},
 541 };
 542
 543 static struct edma_soc_info dm646x_edma_info[] = {
 544         {
 545                 .n_channel              = 64,
 546                 .n_region               = 6,    /* 0-1, 4-7 */
 547                 .n_slot                 = 512,
 548                 .n_tc                   = 4,
 549                 .n_cc                   = 1,
 550                 .noevent                = dma_chan_dm646x_no_event,
 551                 .queue_tc_mapping       = dm646x_queue_tc_mapping,
 552                 .queue_priority_mapping = dm646x_queue_priority_mapping,
 553         },
 554 };
 555
 556 static struct resource edma_resources[] = {
 557         {
 558                 .name   = "edma_cc0",
 559                 .start  = 0x01c00000,
 560                 .end    = 0x01c00000 + SZ_64K - 1,
 561                 .flags  = IORESOURCE_MEM,
 562         },
 563         {
 564                 .name   = "edma_tc0",
 565                 .start  = 0x01c10000,
 566                 .end    = 0x01c10000 + SZ_1K - 1,
 567                 .flags  = IORESOURCE_MEM,
 568         },
 569         {
 570                 .name   = "edma_tc1",
 571                 .start  = 0x01c10400,
 572                 .end    = 0x01c10400 + SZ_1K - 1,
 573                 .flags  = IORESOURCE_MEM,
 574         },
 575         {
 576                 .name   = "edma_tc2",
 577                 .start  = 0x01c10800,
 578                 .end    = 0x01c10800 + SZ_1K - 1,
 579                 .flags  = IORESOURCE_MEM,
 580         },
 581         {
 582                 .name   = "edma_tc3",
 583                 .start  = 0x01c10c00,
 584                 .end    = 0x01c10c00 + SZ_1K - 1,
 585                 .flags  = IORESOURCE_MEM,
 586         },
 587         {
 588                 .name   = "edma0",
 589                 .start  = IRQ_CCINT0,
 590                 .flags  = IORESOURCE_IRQ,
 591         },
 592         {
 593                 .name   = "edma0_err",
 594                 .start  = IRQ_CCERRINT,
 595                 .flags  = IORESOURCE_IRQ,
 596         },
 597         /* not using TC*_ERR */
 598 };
 599
 600 static struct platform_device dm646x_edma_device = {
 601         .name                   = "edma",
 602         .id                     = 0,
 603         .dev.platform_data      = dm646x_edma_info,
 604         .num_resources          = ARRAY_SIZE(edma_resources),
 605         .resource               = edma_resources,
 606 };
 607
 608 static struct resource ide_resources[] = {
 609         {
 610                 .start          = DM646X_ATA_REG_BASE,
 611                 .end            = DM646X_ATA_REG_BASE + 0x7ff,
 612                 .flags          = IORESOURCE_MEM,
 613         },
 614         {
 615                 .start          = IRQ_DM646X_IDE,
 616                 .end            = IRQ_DM646X_IDE,
 617                 .flags          = IORESOURCE_IRQ,
 618         },
 619 };
 620
 621 static u64 ide_dma_mask = DMA_BIT_MASK(32);
 622
 623 static struct platform_device ide_dev = {
 624         .name           = "palm_bk3710",
 625         .id             = -1,
 626         .resource       = ide_resources,
 627         .num_resources  = ARRAY_SIZE(ide_resources),
 628         .dev = {
 629                 .dma_mask               = &ide_dma_mask,
 630                 .coherent_dma_mask      = DMA_BIT_MASK(32),
 631         },
 632 };
 633
 634 static struct resource dm646x_mcasp0_resources[] = {
 635         {
 636                 .name   = "mcasp0",
 637                 .start  = DAVINCI_DM646X_MCASP0_REG_BASE,
 638                 .end    = DAVINCI_DM646X_MCASP0_REG_BASE + (SZ_1K << 1) - 1,
 639                 .flags  = IORESOURCE_MEM,
 640         },
 641         /* first TX, then RX */
 642         {
 643                 .start  = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 644                 .end    = DAVINCI_DM646X_DMA_MCASP0_AXEVT0,
 645                 .flags  = IORESOURCE_DMA,
 646         },
 647         {
 648                 .start  = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 649                 .end    = DAVINCI_DM646X_DMA_MCASP0_AREVT0,
 650                 .flags  = IORESOURCE_DMA,
 651         },
 652 };
 653
 654 static struct resource dm646x_mcasp1_resources[] = {
 655         {
 656                 .name   = "mcasp1",
 657                 .start  = DAVINCI_DM646X_MCASP1_REG_BASE,
 658                 .end    = DAVINCI_DM646X_MCASP1_REG_BASE + (SZ_1K << 1) - 1,
 659                 .flags  = IORESOURCE_MEM,
 660         },
 661         /* DIT mode, only TX event */
 662         {
 663                 .start  = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 664                 .end    = DAVINCI_DM646X_DMA_MCASP1_AXEVT1,
 665                 .flags  = IORESOURCE_DMA,
 666         },
 667         /* DIT mode, dummy entry */
 668         {
 669                 .start  = -1,
 670                 .end    = -1,
 671                 .flags  = IORESOURCE_DMA,
 672         },
 673 };
 674
 675 static struct platform_device dm646x_mcasp0_device = {
 676         .name           = "davinci-mcasp",
 677         .id             = 0,
 678         .num_resources  = ARRAY_SIZE(dm646x_mcasp0_resources),
 679         .resource       = dm646x_mcasp0_resources,
 680 };
 681
 682 static struct platform_device dm646x_mcasp1_device = {
 683         .name           = "davinci-mcasp",
 684         .id             = 1,
 685         .num_resources  = ARRAY_SIZE(dm646x_mcasp1_resources),
 686         .resource       = dm646x_mcasp1_resources,
 687 };
 688
 689 static struct platform_device dm646x_dit_device = {
 690         .name   = "spdif-dit",
 691         .id     = -1,
 692 };
 693
 694 static u64 vpif_dma_mask = DMA_BIT_MASK(32);
 695
 696 static struct resource vpif_resource[] = {
 697         {
 698                 .start  = DAVINCI_VPIF_BASE,
 699                 .end    = DAVINCI_VPIF_BASE + 0x03ff,
 700                 .flags  = IORESOURCE_MEM,
 701         }
 702 };
 703
 704 static struct platform_device vpif_dev = {
 705         .name           = "vpif",
 706         .id             = -1,
 707         .dev            = {
 708                         .dma_mask               = &vpif_dma_mask,
 709                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 710         },
 711         .resource       = vpif_resource,
 712         .num_resources  = ARRAY_SIZE(vpif_resource),
 713 };
 714
 715 static struct resource vpif_display_resource[] = {
 716         {
 717                 .start = IRQ_DM646X_VP_VERTINT2,
 718                 .end   = IRQ_DM646X_VP_VERTINT2,
 719                 .flags = IORESOURCE_IRQ,
 720         },
 721         {
 722                 .start = IRQ_DM646X_VP_VERTINT3,
 723                 .end   = IRQ_DM646X_VP_VERTINT3,
 724                 .flags = IORESOURCE_IRQ,
 725         },
 726 };
 727
 728 static struct platform_device vpif_display_dev = {
 729         .name           = "vpif_display",
 730         .id             = -1,
 731         .dev            = {
 732                         .dma_mask               = &vpif_dma_mask,
 733                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 734         },
 735         .resource       = vpif_display_resource,
 736         .num_resources  = ARRAY_SIZE(vpif_display_resource),
 737 };
 738
 739 static struct resource vpif_capture_resource[] = {
 740         {
 741                 .start = IRQ_DM646X_VP_VERTINT0,
 742                 .end   = IRQ_DM646X_VP_VERTINT0,
 743                 .flags = IORESOURCE_IRQ,
 744         },
 745         {
 746                 .start = IRQ_DM646X_VP_VERTINT1,
 747                 .end   = IRQ_DM646X_VP_VERTINT1,
 748                 .flags = IORESOURCE_IRQ,
 749         },
 750 };
 751
 752 static struct platform_device vpif_capture_dev = {
 753         .name           = "vpif_capture",
 754         .id             = -1,
 755         .dev            = {
 756                         .dma_mask               = &vpif_dma_mask,
 757                         .coherent_dma_mask      = DMA_BIT_MASK(32),
 758         },
 759         .resource       = vpif_capture_resource,
 760         .num_resources  = ARRAY_SIZE(vpif_capture_resource),
 761 };
 762
 763 /*----------------------------------------------------------------------*/
 764
 765 static struct map_desc dm646x_io_desc[] = {
 766         {
 767                 .virtual        = IO_VIRT,
 768                 .pfn            = __phys_to_pfn(IO_PHYS),
 769                 .length         = IO_SIZE,
 770                 .type           = MT_DEVICE
 771         },
 772         {
 773                 .virtual        = SRAM_VIRT,
 774                 .pfn            = __phys_to_pfn(0x00010000),
 775                 .length         = SZ_32K,
 776                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 777                 .type           = MT_DEVICE,
 778         },
 779 };
 780
 781 /* Contents of JTAG ID register used to identify exact cpu type */
 782 static struct davinci_id dm646x_ids[] = {
 783         {
 784                 .variant        = 0x0,
 785                 .part_no        = 0xb770,
 786                 .manufacturer   = 0x017,
 787                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 788                 .name           = "dm6467_rev1.x",
 789         },
 790         {
 791                 .variant        = 0x1,
 792                 .part_no        = 0xb770,
 793                 .manufacturer   = 0x017,
 794                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 795                 .name           = "dm6467_rev3.x",
 796         },
 797 };
 798
 799 static void __iomem *dm646x_psc_bases[] = {
 800         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 801 };
 802
 803 /*
 804  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 805  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 806  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 807  * T1_TOP: Timer 1, top   :  <unused>
 808  */
 809 struct davinci_timer_info dm646x_timer_info = {
 810         .timers         = davinci_timer_instance,
 811         .clockevent_id  = T0_BOT,
 812         .clocksource_id = T0_TOP,
 813 };
 814
 815 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 816         {
 817                 .mapbase        = DAVINCI_UART0_BASE,
 818                 .irq            = IRQ_UARTINT0,
 819                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 820                                   UPF_IOREMAP,
 821                 .iotype         = UPIO_MEM32,
 822                 .regshift       = 2,
 823         },
 824         {
 825                 .mapbase        = DAVINCI_UART1_BASE,
 826                 .irq            = IRQ_UARTINT1,
 827                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 828                                   UPF_IOREMAP,
 829                 .iotype         = UPIO_MEM32,
 830                 .regshift       = 2,
 831         },
 832         {
 833                 .mapbase        = DAVINCI_UART2_BASE,
 834                 .irq            = IRQ_DM646X_UARTINT2,
 835                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 836                                   UPF_IOREMAP,
 837                 .iotype         = UPIO_MEM32,
 838                 .regshift       = 2,
 839         },
 840         {
 841                 .flags          = 0
 842         },
 843 };
 844
 845 static struct platform_device dm646x_serial_device = {
 846         .name                   = "serial8250",
 847         .id                     = PLAT8250_DEV_PLATFORM,
 848         .dev                    = {
 849                 .platform_data  = dm646x_serial_platform_data,
 850         },
 851 };
 852
 853 static struct davinci_soc_info davinci_soc_info_dm646x = {
 854         .io_desc                = dm646x_io_desc,
 855         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 856         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 857         .ids                    = dm646x_ids,
 858         .ids_num                = ARRAY_SIZE(dm646x_ids),
 859         .cpu_clks               = dm646x_clks,
 860         .psc_bases              = dm646x_psc_bases,
 861         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 862         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 863         .pinmux_pins            = dm646x_pins,
 864         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 865         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 866         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 867         .intc_irq_prios         = dm646x_default_priorities,
 868         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 869         .timer_info             = &dm646x_timer_info,
 870         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 871         .gpio_num               = 43, /* Only 33 usable */
 872         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 873         .serial_dev             = &dm646x_serial_device,
 874         .emac_pdata             = &dm646x_emac_pdata,
 875         .sram_dma               = 0x10010000,
 876         .sram_len               = SZ_32K,
 877 };
 878
 879 void __init dm646x_init_ide()
 880 {
 881         davinci_cfg_reg(DM646X_ATAEN);
 882         platform_device_register(&ide_dev);
 883 }
 884
 885 void __init dm646x_init_mcasp0(struct snd_platform_data *pdata)
 886 {
 887         dm646x_mcasp0_device.dev.platform_data = pdata;
 888         platform_device_register(&dm646x_mcasp0_device);
 889 }
 890
 891 void __init dm646x_init_mcasp1(struct snd_platform_data *pdata)
 892 {
 893         dm646x_mcasp1_device.dev.platform_data = pdata;
 894         platform_device_register(&dm646x_mcasp1_device);
 895         platform_device_register(&dm646x_dit_device);
 896 }
 897
 898 void dm646x_setup_vpif(struct vpif_display_config *display_config,
 899                        struct vpif_capture_config *capture_config)
 900 {
 901         unsigned int value;
 902         void __iomem *base = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE);
 903
 904         value = __raw_readl(base + VSCLKDIS_OFFSET);
 905         value &= ~VSCLKDIS_MASK;
 906         __raw_writel(value, base + VSCLKDIS_OFFSET);
 907
 908         value = __raw_readl(base + VDD3P3V_PWDN_OFFSET);
 909         value &= ~VDD3P3V_VID_MASK;
 910         __raw_writel(value, base + VDD3P3V_PWDN_OFFSET);
 911
 912         davinci_cfg_reg(DM646X_STSOMUX_DISABLE);
 913         davinci_cfg_reg(DM646X_STSIMUX_DISABLE);
 914         davinci_cfg_reg(DM646X_PTSOMUX_DISABLE);
 915         davinci_cfg_reg(DM646X_PTSIMUX_DISABLE);
 916
 917         vpif_display_dev.dev.platform_data = display_config;
 918         vpif_capture_dev.dev.platform_data = capture_config;
 919         platform_device_register(&vpif_dev);
 920         platform_device_register(&vpif_display_dev);
 921         platform_device_register(&vpif_capture_dev);
 922 }
 923
 924 void __init dm646x_init(void)
 925 {
 926         dm646x_board_setup_refclk(&ref_clk);
 927         davinci_common_init(&davinci_soc_info_dm646x);
 928 }
 929
 930 static int __init dm646x_init_devices(void)
 931 {
 932         if (!cpu_is_davinci_dm646x())
 933                 return 0;
 934
 935         platform_device_register(&dm646x_edma_device);
 936         platform_device_register(&dm646x_emac_device);
 937         return 0;
 938 }
 939 postcore_initcall(dm646x_init_devices);