SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-davinci/dm646x.c

   1 /*
   2  * TI DaVinci DM644x chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/serial_8250.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/gpio.h>
  17
  18 #include <asm/mach/map.h>
  19
  20 #include <mach/dm646x.h>
  21 #include <mach/clock.h>
  22 #include <mach/cputype.h>
  23 #include <mach/edma.h>
  24 #include <mach/irqs.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/time.h>
  28 #include <mach/serial.h>
  29 #include <mach/common.h>
  30
  31 #include "clock.h"
  32 #include "mux.h"
  33
  34 /*
  35  * Device specific clocks
  36  */
  37 #define DM646X_REF_FREQ         27000000
  38 #define DM646X_AUX_FREQ         24000000
  39
  40 static struct pll_data pll1_data = {
  41         .num       = 1,
  42         .phys_base = DAVINCI_PLL1_BASE,
  43 };
  44
  45 static struct pll_data pll2_data = {
  46         .num       = 2,
  47         .phys_base = DAVINCI_PLL2_BASE,
  48 };
  49
  50 static struct clk ref_clk = {
  51         .name = "ref_clk",
  52         .rate = DM646X_REF_FREQ,
  53 };
  54
  55 static struct clk aux_clkin = {
  56         .name = "aux_clkin",
  57         .rate = DM646X_AUX_FREQ,
  58 };
  59
  60 static struct clk pll1_clk = {
  61         .name = "pll1",
  62         .parent = &ref_clk,
  63         .pll_data = &pll1_data,
  64         .flags = CLK_PLL,
  65 };
  66
  67 static struct clk pll1_sysclk1 = {
  68         .name = "pll1_sysclk1",
  69         .parent = &pll1_clk,
  70         .flags = CLK_PLL,
  71         .div_reg = PLLDIV1,
  72 };
  73
  74 static struct clk pll1_sysclk2 = {
  75         .name = "pll1_sysclk2",
  76         .parent = &pll1_clk,
  77         .flags = CLK_PLL,
  78         .div_reg = PLLDIV2,
  79 };
  80
  81 static struct clk pll1_sysclk3 = {
  82         .name = "pll1_sysclk3",
  83         .parent = &pll1_clk,
  84         .flags = CLK_PLL,
  85         .div_reg = PLLDIV3,
  86 };
  87
  88 static struct clk pll1_sysclk4 = {
  89         .name = "pll1_sysclk4",
  90         .parent = &pll1_clk,
  91         .flags = CLK_PLL,
  92         .div_reg = PLLDIV4,
  93 };
  94
  95 static struct clk pll1_sysclk5 = {
  96         .name = "pll1_sysclk5",
  97         .parent = &pll1_clk,
  98         .flags = CLK_PLL,
  99         .div_reg = PLLDIV5,
 100 };
 101
 102 static struct clk pll1_sysclk6 = {
 103         .name = "pll1_sysclk6",
 104         .parent = &pll1_clk,
 105         .flags = CLK_PLL,
 106         .div_reg = PLLDIV6,
 107 };
 108
 109 static struct clk pll1_sysclk8 = {
 110         .name = "pll1_sysclk8",
 111         .parent = &pll1_clk,
 112         .flags = CLK_PLL,
 113         .div_reg = PLLDIV8,
 114 };
 115
 116 static struct clk pll1_sysclk9 = {
 117         .name = "pll1_sysclk9",
 118         .parent = &pll1_clk,
 119         .flags = CLK_PLL,
 120         .div_reg = PLLDIV9,
 121 };
 122
 123 static struct clk pll1_sysclkbp = {
 124         .name = "pll1_sysclkbp",
 125         .parent = &pll1_clk,
 126         .flags = CLK_PLL | PRE_PLL,
 127         .div_reg = BPDIV,
 128 };
 129
 130 static struct clk pll1_aux_clk = {
 131         .name = "pll1_aux_clk",
 132         .parent = &pll1_clk,
 133         .flags = CLK_PLL | PRE_PLL,
 134 };
 135
 136 static struct clk pll2_clk = {
 137         .name = "pll2_clk",
 138         .parent = &ref_clk,
 139         .pll_data = &pll2_data,
 140         .flags = CLK_PLL,
 141 };
 142
 143 static struct clk pll2_sysclk1 = {
 144         .name = "pll2_sysclk1",
 145         .parent = &pll2_clk,
 146         .flags = CLK_PLL,
 147         .div_reg = PLLDIV1,
 148 };
 149
 150 static struct clk dsp_clk = {
 151         .name = "dsp",
 152         .parent = &pll1_sysclk1,
 153         .lpsc = DM646X_LPSC_C64X_CPU,
 154         .flags = PSC_DSP,
 155         .usecount = 1,                  /* REVISIT how to disable? */
 156 };
 157
 158 static struct clk arm_clk = {
 159         .name = "arm",
 160         .parent = &pll1_sysclk2,
 161         .lpsc = DM646X_LPSC_ARM,
 162         .flags = ALWAYS_ENABLED,
 163 };
 164
 165 static struct clk edma_cc_clk = {
 166         .name = "edma_cc",
 167         .parent = &pll1_sysclk2,
 168         .lpsc = DM646X_LPSC_TPCC,
 169         .flags = ALWAYS_ENABLED,
 170 };
 171
 172 static struct clk edma_tc0_clk = {
 173         .name = "edma_tc0",
 174         .parent = &pll1_sysclk2,
 175         .lpsc = DM646X_LPSC_TPTC0,
 176         .flags = ALWAYS_ENABLED,
 177 };
 178
 179 static struct clk edma_tc1_clk = {
 180         .name = "edma_tc1",
 181         .parent = &pll1_sysclk2,
 182         .lpsc = DM646X_LPSC_TPTC1,
 183         .flags = ALWAYS_ENABLED,
 184 };
 185
 186 static struct clk edma_tc2_clk = {
 187         .name = "edma_tc2",
 188         .parent = &pll1_sysclk2,
 189         .lpsc = DM646X_LPSC_TPTC2,
 190         .flags = ALWAYS_ENABLED,
 191 };
 192
 193 static struct clk edma_tc3_clk = {
 194         .name = "edma_tc3",
 195         .parent = &pll1_sysclk2,
 196         .lpsc = DM646X_LPSC_TPTC3,
 197         .flags = ALWAYS_ENABLED,
 198 };
 199
 200 static struct clk uart0_clk = {
 201         .name = "uart0",
 202         .parent = &aux_clkin,
 203         .lpsc = DM646X_LPSC_UART0,
 204 };
 205
 206 static struct clk uart1_clk = {
 207         .name = "uart1",
 208         .parent = &aux_clkin,
 209         .lpsc = DM646X_LPSC_UART1,
 210 };
 211
 212 static struct clk uart2_clk = {
 213         .name = "uart2",
 214         .parent = &aux_clkin,
 215         .lpsc = DM646X_LPSC_UART2,
 216 };
 217
 218 static struct clk i2c_clk = {
 219         .name = "I2CCLK",
 220         .parent = &pll1_sysclk3,
 221         .lpsc = DM646X_LPSC_I2C,
 222 };
 223
 224 static struct clk gpio_clk = {
 225         .name = "gpio",
 226         .parent = &pll1_sysclk3,
 227         .lpsc = DM646X_LPSC_GPIO,
 228 };
 229
 230 static struct clk aemif_clk = {
 231         .name = "aemif",
 232         .parent = &pll1_sysclk3,
 233         .lpsc = DM646X_LPSC_AEMIF,
 234         .flags = ALWAYS_ENABLED,
 235 };
 236
 237 static struct clk emac_clk = {
 238         .name = "emac",
 239         .parent = &pll1_sysclk3,
 240         .lpsc = DM646X_LPSC_EMAC,
 241 };
 242
 243 static struct clk pwm0_clk = {
 244         .name = "pwm0",
 245         .parent = &pll1_sysclk3,
 246         .lpsc = DM646X_LPSC_PWM0,
 247         .usecount = 1,            /* REVIST: disabling hangs system */
 248 };
 249
 250 static struct clk pwm1_clk = {
 251         .name = "pwm1",
 252         .parent = &pll1_sysclk3,
 253         .lpsc = DM646X_LPSC_PWM1,
 254         .usecount = 1,            /* REVIST: disabling hangs system */
 255 };
 256
 257 static struct clk timer0_clk = {
 258         .name = "timer0",
 259         .parent = &pll1_sysclk3,
 260         .lpsc = DM646X_LPSC_TIMER0,
 261 };
 262
 263 static struct clk timer1_clk = {
 264         .name = "timer1",
 265         .parent = &pll1_sysclk3,
 266         .lpsc = DM646X_LPSC_TIMER1,
 267 };
 268
 269 static struct clk timer2_clk = {
 270         .name = "timer2",
 271         .parent = &pll1_sysclk3,
 272         .flags = ALWAYS_ENABLED, /* no LPSC, always enabled; c.f. spruep9a */
 273 };
 274
 275 static struct clk vpif0_clk = {
 276         .name = "vpif0",
 277         .parent = &ref_clk,
 278         .lpsc = DM646X_LPSC_VPSSMSTR,
 279         .flags = ALWAYS_ENABLED,
 280 };
 281
 282 static struct clk vpif1_clk = {
 283         .name = "vpif1",
 284         .parent = &ref_clk,
 285         .lpsc = DM646X_LPSC_VPSSSLV,
 286         .flags = ALWAYS_ENABLED,
 287 };
 288
 289 struct davinci_clk dm646x_clks[] = {
 290         CLK(NULL, "ref", &ref_clk),
 291         CLK(NULL, "aux", &aux_clkin),
 292         CLK(NULL, "pll1", &pll1_clk),
 293         CLK(NULL, "pll1_sysclk", &pll1_sysclk1),
 294         CLK(NULL, "pll1_sysclk", &pll1_sysclk2),
 295         CLK(NULL, "pll1_sysclk", &pll1_sysclk3),
 296         CLK(NULL, "pll1_sysclk", &pll1_sysclk4),
 297         CLK(NULL, "pll1_sysclk", &pll1_sysclk5),
 298         CLK(NULL, "pll1_sysclk", &pll1_sysclk6),
 299         CLK(NULL, "pll1_sysclk", &pll1_sysclk8),
 300         CLK(NULL, "pll1_sysclk", &pll1_sysclk9),
 301         CLK(NULL, "pll1_sysclk", &pll1_sysclkbp),
 302         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 303         CLK(NULL, "pll2", &pll2_clk),
 304         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 305         CLK(NULL, "dsp", &dsp_clk),
 306         CLK(NULL, "arm", &arm_clk),
 307         CLK(NULL, "edma_cc", &edma_cc_clk),
 308         CLK(NULL, "edma_tc0", &edma_tc0_clk),
 309         CLK(NULL, "edma_tc1", &edma_tc1_clk),
 310         CLK(NULL, "edma_tc2", &edma_tc2_clk),
 311         CLK(NULL, "edma_tc3", &edma_tc3_clk),
 312         CLK(NULL, "uart0", &uart0_clk),
 313         CLK(NULL, "uart1", &uart1_clk),
 314         CLK(NULL, "uart2", &uart2_clk),
 315         CLK("i2c_davinci.1", NULL, &i2c_clk),
 316         CLK(NULL, "gpio", &gpio_clk),
 317         CLK(NULL, "aemif", &aemif_clk),
 318         CLK("davinci_emac.1", NULL, &emac_clk),
 319         CLK(NULL, "pwm0", &pwm0_clk),
 320         CLK(NULL, "pwm1", &pwm1_clk),
 321         CLK(NULL, "timer0", &timer0_clk),
 322         CLK(NULL, "timer1", &timer1_clk),
 323         CLK("watchdog", NULL, &timer2_clk),
 324         CLK(NULL, "vpif0", &vpif0_clk),
 325         CLK(NULL, "vpif1", &vpif1_clk),
 326         CLK(NULL, NULL, NULL),
 327 };
 328
 329 static struct emac_platform_data dm646x_emac_pdata = {
 330         .ctrl_reg_offset        = DM646X_EMAC_CNTRL_OFFSET,
 331         .ctrl_mod_reg_offset    = DM646X_EMAC_CNTRL_MOD_OFFSET,
 332         .ctrl_ram_offset        = DM646X_EMAC_CNTRL_RAM_OFFSET,
 333         .mdio_reg_offset        = DM646X_EMAC_MDIO_OFFSET,
 334         .ctrl_ram_size          = DM646X_EMAC_CNTRL_RAM_SIZE,
 335         .version                = EMAC_VERSION_2,
 336 };
 337
 338 static struct resource dm646x_emac_resources[] = {
 339         {
 340                 .start  = DM646X_EMAC_BASE,
 341                 .end    = DM646X_EMAC_BASE + 0x47ff,
 342                 .flags  = IORESOURCE_MEM,
 343         },
 344         {
 345                 .start  = IRQ_DM646X_EMACRXTHINT,
 346                 .end    = IRQ_DM646X_EMACRXTHINT,
 347                 .flags  = IORESOURCE_IRQ,
 348         },
 349         {
 350                 .start  = IRQ_DM646X_EMACRXINT,
 351                 .end    = IRQ_DM646X_EMACRXINT,
 352                 .flags  = IORESOURCE_IRQ,
 353         },
 354         {
 355                 .start  = IRQ_DM646X_EMACTXINT,
 356                 .end    = IRQ_DM646X_EMACTXINT,
 357                 .flags  = IORESOURCE_IRQ,
 358         },
 359         {
 360                 .start  = IRQ_DM646X_EMACMISCINT,
 361                 .end    = IRQ_DM646X_EMACMISCINT,
 362                 .flags  = IORESOURCE_IRQ,
 363         },
 364 };
 365
 366 static struct platform_device dm646x_emac_device = {
 367         .name           = "davinci_emac",
 368         .id             = 1,
 369         .dev = {
 370                 .platform_data  = &dm646x_emac_pdata,
 371         },
 372         .num_resources  = ARRAY_SIZE(dm646x_emac_resources),
 373         .resource       = dm646x_emac_resources,
 374 };
 375
 376 #define PINMUX0         0x00
 377 #define PINMUX1         0x04
 378
 379 /*
 380  * Device specific mux setup
 381  *
 382  *      soc     description     mux  mode   mode  mux    dbg
 383  *                              reg  offset mask  mode
 384  */
 385 static const struct mux_config dm646x_pins[] = {
 386 #ifdef CONFIG_DAVINCI_MUX
 387 MUX_CFG(DM646X, ATAEN,          0,   0,     1,    1,     true)
 388
 389 MUX_CFG(DM646X, AUDCK1,         0,   29,    1,    0,     false)
 390
 391 MUX_CFG(DM646X, AUDCK0,         0,   28,    1,    0,     false)
 392
 393 MUX_CFG(DM646X, CRGMUX,                 0,   24,    7,    5,     true)
 394
 395 MUX_CFG(DM646X, STSOMUX_DISABLE,        0,   22,    3,    0,     true)
 396
 397 MUX_CFG(DM646X, STSIMUX_DISABLE,        0,   20,    3,    0,     true)
 398
 399 MUX_CFG(DM646X, PTSOMUX_DISABLE,        0,   18,    3,    0,     true)
 400
 401 MUX_CFG(DM646X, PTSIMUX_DISABLE,        0,   16,    3,    0,     true)
 402
 403 MUX_CFG(DM646X, STSOMUX,                0,   22,    3,    2,     true)
 404
 405 MUX_CFG(DM646X, STSIMUX,                0,   20,    3,    2,     true)
 406
 407 MUX_CFG(DM646X, PTSOMUX_PARALLEL,       0,   18,    3,    2,     true)
 408
 409 MUX_CFG(DM646X, PTSIMUX_PARALLEL,       0,   16,    3,    2,     true)
 410
 411 MUX_CFG(DM646X, PTSOMUX_SERIAL,         0,   18,    3,    3,     true)
 412
 413 MUX_CFG(DM646X, PTSIMUX_SERIAL,         0,   16,    3,    3,     true)
 414 #endif
 415 };
 416
 417 static u8 dm646x_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 418         [IRQ_DM646X_VP_VERTINT0]        = 7,
 419         [IRQ_DM646X_VP_VERTINT1]        = 7,
 420         [IRQ_DM646X_VP_VERTINT2]        = 7,
 421         [IRQ_DM646X_VP_VERTINT3]        = 7,
 422         [IRQ_DM646X_VP_ERRINT]          = 7,
 423         [IRQ_DM646X_RESERVED_1]         = 7,
 424         [IRQ_DM646X_RESERVED_2]         = 7,
 425         [IRQ_DM646X_WDINT]              = 7,
 426         [IRQ_DM646X_CRGENINT0]          = 7,
 427         [IRQ_DM646X_CRGENINT1]          = 7,
 428         [IRQ_DM646X_TSIFINT0]           = 7,
 429         [IRQ_DM646X_TSIFINT1]           = 7,
 430         [IRQ_DM646X_VDCEINT]            = 7,
 431         [IRQ_DM646X_USBINT]             = 7,
 432         [IRQ_DM646X_USBDMAINT]          = 7,
 433         [IRQ_DM646X_PCIINT]             = 7,
 434         [IRQ_CCINT0]                    = 7,    /* dma */
 435         [IRQ_CCERRINT]                  = 7,    /* dma */
 436         [IRQ_TCERRINT0]                 = 7,    /* dma */
 437         [IRQ_TCERRINT]                  = 7,    /* dma */
 438         [IRQ_DM646X_TCERRINT2]          = 7,
 439         [IRQ_DM646X_TCERRINT3]          = 7,
 440         [IRQ_DM646X_IDE]                = 7,
 441         [IRQ_DM646X_HPIINT]             = 7,
 442         [IRQ_DM646X_EMACRXTHINT]        = 7,
 443         [IRQ_DM646X_EMACRXINT]          = 7,
 444         [IRQ_DM646X_EMACTXINT]          = 7,
 445         [IRQ_DM646X_EMACMISCINT]        = 7,
 446         [IRQ_DM646X_MCASP0TXINT]        = 7,
 447         [IRQ_DM646X_MCASP0RXINT]        = 7,
 448         [IRQ_AEMIFINT]                  = 7,
 449         [IRQ_DM646X_RESERVED_3]         = 7,
 450         [IRQ_DM646X_MCASP1TXINT]        = 7,    /* clockevent */
 451         [IRQ_TINT0_TINT34]              = 7,    /* clocksource */
 452         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 453         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 454         [IRQ_PWMINT0]                   = 7,
 455         [IRQ_PWMINT1]                   = 7,
 456         [IRQ_DM646X_VLQINT]             = 7,
 457         [IRQ_I2C]                       = 7,
 458         [IRQ_UARTINT0]                  = 7,
 459         [IRQ_UARTINT1]                  = 7,
 460         [IRQ_DM646X_UARTINT2]           = 7,
 461         [IRQ_DM646X_SPINT0]             = 7,
 462         [IRQ_DM646X_SPINT1]             = 7,
 463         [IRQ_DM646X_DSP2ARMINT]         = 7,
 464         [IRQ_DM646X_RESERVED_4]         = 7,
 465         [IRQ_DM646X_PSCINT]             = 7,
 466         [IRQ_DM646X_GPIO0]              = 7,
 467         [IRQ_DM646X_GPIO1]              = 7,
 468         [IRQ_DM646X_GPIO2]              = 7,
 469         [IRQ_DM646X_GPIO3]              = 7,
 470         [IRQ_DM646X_GPIO4]              = 7,
 471         [IRQ_DM646X_GPIO5]              = 7,
 472         [IRQ_DM646X_GPIO6]              = 7,
 473         [IRQ_DM646X_GPIO7]              = 7,
 474         [IRQ_DM646X_GPIOBNK0]           = 7,
 475         [IRQ_DM646X_GPIOBNK1]           = 7,
 476         [IRQ_DM646X_GPIOBNK2]           = 7,
 477         [IRQ_DM646X_DDRINT]             = 7,
 478         [IRQ_DM646X_AEMIFINT]           = 7,
 479         [IRQ_COMMTX]                    = 7,
 480         [IRQ_COMMRX]                    = 7,
 481         [IRQ_EMUINT]                    = 7,
 482 };
 483
 484 /*----------------------------------------------------------------------*/
 485
 486 static const s8 dma_chan_dm646x_no_event[] = {
 487          0,  1,  2,  3, 13,
 488         14, 15, 24, 25, 26,
 489         27, 30, 31, 54, 55,
 490         56,
 491         -1
 492 };
 493
 494 /* Four Transfer Controllers on DM646x */
 495 static const s8
 496 dm646x_queue_tc_mapping[][2] = {
 497         /* {event queue no, TC no} */
 498         {0, 0},
 499         {1, 1},
 500         {2, 2},
 501         {3, 3},
 502         {-1, -1},
 503 };
 504
 505 static const s8
 506 dm646x_queue_priority_mapping[][2] = {
 507         /* {event queue no, Priority} */
 508         {0, 4},
 509         {1, 0},
 510         {2, 5},
 511         {3, 1},
 512         {-1, -1},
 513 };
 514
 515 static struct edma_soc_info dm646x_edma_info[] = {
 516         {
 517                 .n_channel              = 64,
 518                 .n_region               = 6,    /* 0-1, 4-7 */
 519                 .n_slot                 = 512,
 520                 .n_tc                   = 4,
 521                 .n_cc                   = 1,
 522                 .noevent                = dma_chan_dm646x_no_event,
 523                 .queue_tc_mapping       = dm646x_queue_tc_mapping,
 524                 .queue_priority_mapping = dm646x_queue_priority_mapping,
 525         },
 526 };
 527
 528 static struct resource edma_resources[] = {
 529         {
 530                 .name   = "edma_cc0",
 531                 .start  = 0x01c00000,
 532                 .end    = 0x01c00000 + SZ_64K - 1,
 533                 .flags  = IORESOURCE_MEM,
 534         },
 535         {
 536                 .name   = "edma_tc0",
 537                 .start  = 0x01c10000,
 538                 .end    = 0x01c10000 + SZ_1K - 1,
 539                 .flags  = IORESOURCE_MEM,
 540         },
 541         {
 542                 .name   = "edma_tc1",
 543                 .start  = 0x01c10400,
 544                 .end    = 0x01c10400 + SZ_1K - 1,
 545                 .flags  = IORESOURCE_MEM,
 546         },
 547         {
 548                 .name   = "edma_tc2",
 549                 .start  = 0x01c10800,
 550                 .end    = 0x01c10800 + SZ_1K - 1,
 551                 .flags  = IORESOURCE_MEM,
 552         },
 553         {
 554                 .name   = "edma_tc3",
 555                 .start  = 0x01c10c00,
 556                 .end    = 0x01c10c00 + SZ_1K - 1,
 557                 .flags  = IORESOURCE_MEM,
 558         },
 559         {
 560                 .name   = "edma0",
 561                 .start  = IRQ_CCINT0,
 562                 .flags  = IORESOURCE_IRQ,
 563         },
 564         {
 565                 .name   = "edma0_err",
 566                 .start  = IRQ_CCERRINT,
 567                 .flags  = IORESOURCE_IRQ,
 568         },
 569         /* not using TC*_ERR */
 570 };
 571
 572 static struct platform_device dm646x_edma_device = {
 573         .name                   = "edma",
 574         .id                     = 0,
 575         .dev.platform_data      = dm646x_edma_info,
 576         .num_resources          = ARRAY_SIZE(edma_resources),
 577         .resource               = edma_resources,
 578 };
 579
 580 /*----------------------------------------------------------------------*/
 581
 582 static struct map_desc dm646x_io_desc[] = {
 583         {
 584                 .virtual        = IO_VIRT,
 585                 .pfn            = __phys_to_pfn(IO_PHYS),
 586                 .length         = IO_SIZE,
 587                 .type           = MT_DEVICE
 588         },
 589         {
 590                 .virtual        = SRAM_VIRT,
 591                 .pfn            = __phys_to_pfn(0x00010000),
 592                 .length         = SZ_32K,
 593                 /* MT_MEMORY_NONCACHED requires supersection alignment */
 594                 .type           = MT_DEVICE,
 595         },
 596 };
 597
 598 /* Contents of JTAG ID register used to identify exact cpu type */
 599 static struct davinci_id dm646x_ids[] = {
 600         {
 601                 .variant        = 0x0,
 602                 .part_no        = 0xb770,
 603                 .manufacturer   = 0x017,
 604                 .cpu_id         = DAVINCI_CPU_ID_DM6467,
 605                 .name           = "dm6467",
 606         },
 607 };
 608
 609 static void __iomem *dm646x_psc_bases[] = {
 610         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 611 };
 612
 613 /*
 614  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 615  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 616  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 617  * T1_TOP: Timer 1, top   :  <unused>
 618  */
 619 struct davinci_timer_info dm646x_timer_info = {
 620         .timers         = davinci_timer_instance,
 621         .clockevent_id  = T0_BOT,
 622         .clocksource_id = T0_TOP,
 623 };
 624
 625 static struct plat_serial8250_port dm646x_serial_platform_data[] = {
 626         {
 627                 .mapbase        = DAVINCI_UART0_BASE,
 628                 .irq            = IRQ_UARTINT0,
 629                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 630                                   UPF_IOREMAP,
 631                 .iotype         = UPIO_MEM32,
 632                 .regshift       = 2,
 633         },
 634         {
 635                 .mapbase        = DAVINCI_UART1_BASE,
 636                 .irq            = IRQ_UARTINT1,
 637                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 638                                   UPF_IOREMAP,
 639                 .iotype         = UPIO_MEM32,
 640                 .regshift       = 2,
 641         },
 642         {
 643                 .mapbase        = DAVINCI_UART2_BASE,
 644                 .irq            = IRQ_DM646X_UARTINT2,
 645                 .flags          = UPF_BOOT_AUTOCONF | UPF_SKIP_TEST |
 646                                   UPF_IOREMAP,
 647                 .iotype         = UPIO_MEM32,
 648                 .regshift       = 2,
 649         },
 650         {
 651                 .flags          = 0
 652         },
 653 };
 654
 655 static struct platform_device dm646x_serial_device = {
 656         .name                   = "serial8250",
 657         .id                     = PLAT8250_DEV_PLATFORM,
 658         .dev                    = {
 659                 .platform_data  = dm646x_serial_platform_data,
 660         },
 661 };
 662
 663 static struct davinci_soc_info davinci_soc_info_dm646x = {
 664         .io_desc                = dm646x_io_desc,
 665         .io_desc_num            = ARRAY_SIZE(dm646x_io_desc),
 666         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 667         .ids                    = dm646x_ids,
 668         .ids_num                = ARRAY_SIZE(dm646x_ids),
 669         .cpu_clks               = dm646x_clks,
 670         .psc_bases              = dm646x_psc_bases,
 671         .psc_bases_num          = ARRAY_SIZE(dm646x_psc_bases),
 672         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 673         .pinmux_pins            = dm646x_pins,
 674         .pinmux_pins_num        = ARRAY_SIZE(dm646x_pins),
 675         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 676         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 677         .intc_irq_prios         = dm646x_default_priorities,
 678         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 679         .timer_info             = &dm646x_timer_info,
 680         .wdt_base               = IO_ADDRESS(DAVINCI_WDOG_BASE),
 681         .gpio_base              = IO_ADDRESS(DAVINCI_GPIO_BASE),
 682         .gpio_num               = 43, /* Only 33 usable */
 683         .gpio_irq               = IRQ_DM646X_GPIOBNK0,
 684         .serial_dev             = &dm646x_serial_device,
 685         .emac_pdata             = &dm646x_emac_pdata,
 686         .sram_dma               = 0x10010000,
 687         .sram_len               = SZ_32K,
 688 };
 689
 690 void __init dm646x_init(void)
 691 {
 692         davinci_common_init(&davinci_soc_info_dm646x);
 693 }
 694
 695 static int __init dm646x_init_devices(void)
 696 {
 697         if (!cpu_is_davinci_dm646x())
 698                 return 0;
 699
 700         platform_device_register(&dm646x_edma_device);
 701         platform_device_register(&dm646x_emac_device);
 702         return 0;
 703 }
 704 postcore_initcall(dm646x_init_devices);