SAFE public projects git trees. - safe/jmp/linux-2.6/blob - arch/arm/mach-davinci/dm355.c

   1 /*
   2  * TI DaVinci DM355 chip specific setup
   3  *
   4  * Author: Kevin Hilman, Deep Root Systems, LLC
   5  *
   6  * 2007 (c) Deep Root Systems, LLC. This file is licensed under
   7  * the terms of the GNU General Public License version 2. This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11 #include <linux/kernel.h>
  12 #include <linux/init.h>
  13 #include <linux/clk.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/dma-mapping.h>
  16
  17 #include <linux/spi/spi.h>
  18
  19 #include <asm/mach/map.h>
  20
  21 #include <mach/dm355.h>
  22 #include <mach/clock.h>
  23 #include <mach/cputype.h>
  24 #include <mach/edma.h>
  25 #include <mach/psc.h>
  26 #include <mach/mux.h>
  27 #include <mach/irqs.h>
  28 #include <mach/time.h>
  29 #include <mach/common.h>
  30
  31 #include "clock.h"
  32 #include "mux.h"
  33
  34 /*
  35  * Device specific clocks
  36  */
  37 #define DM355_REF_FREQ          24000000        /* 24 or 36 MHz */
  38
  39 static struct pll_data pll1_data = {
  40         .num       = 1,
  41         .phys_base = DAVINCI_PLL1_BASE,
  42         .flags     = PLL_HAS_PREDIV | PLL_HAS_POSTDIV,
  43 };
  44
  45 static struct pll_data pll2_data = {
  46         .num       = 2,
  47         .phys_base = DAVINCI_PLL2_BASE,
  48         .flags     = PLL_HAS_PREDIV,
  49 };
  50
  51 static struct clk ref_clk = {
  52         .name = "ref_clk",
  53         /* FIXME -- crystal rate is board-specific */
  54         .rate = DM355_REF_FREQ,
  55 };
  56
  57 static struct clk pll1_clk = {
  58         .name = "pll1",
  59         .parent = &ref_clk,
  60         .flags = CLK_PLL,
  61         .pll_data = &pll1_data,
  62 };
  63
  64 static struct clk pll1_aux_clk = {
  65         .name = "pll1_aux_clk",
  66         .parent = &pll1_clk,
  67         .flags = CLK_PLL | PRE_PLL,
  68 };
  69
  70 static struct clk pll1_sysclk1 = {
  71         .name = "pll1_sysclk1",
  72         .parent = &pll1_clk,
  73         .flags = CLK_PLL,
  74         .div_reg = PLLDIV1,
  75 };
  76
  77 static struct clk pll1_sysclk2 = {
  78         .name = "pll1_sysclk2",
  79         .parent = &pll1_clk,
  80         .flags = CLK_PLL,
  81         .div_reg = PLLDIV2,
  82 };
  83
  84 static struct clk pll1_sysclk3 = {
  85         .name = "pll1_sysclk3",
  86         .parent = &pll1_clk,
  87         .flags = CLK_PLL,
  88         .div_reg = PLLDIV3,
  89 };
  90
  91 static struct clk pll1_sysclk4 = {
  92         .name = "pll1_sysclk4",
  93         .parent = &pll1_clk,
  94         .flags = CLK_PLL,
  95         .div_reg = PLLDIV4,
  96 };
  97
  98 static struct clk pll1_sysclkbp = {
  99         .name = "pll1_sysclkbp",
 100         .parent = &pll1_clk,
 101         .flags = CLK_PLL | PRE_PLL,
 102         .div_reg = BPDIV
 103 };
 104
 105 static struct clk vpss_dac_clk = {
 106         .name = "vpss_dac",
 107         .parent = &pll1_sysclk3,
 108         .lpsc = DM355_LPSC_VPSS_DAC,
 109 };
 110
 111 static struct clk vpss_master_clk = {
 112         .name = "vpss_master",
 113         .parent = &pll1_sysclk4,
 114         .lpsc = DAVINCI_LPSC_VPSSMSTR,
 115         .flags = CLK_PSC,
 116 };
 117
 118 static struct clk vpss_slave_clk = {
 119         .name = "vpss_slave",
 120         .parent = &pll1_sysclk4,
 121         .lpsc = DAVINCI_LPSC_VPSSSLV,
 122 };
 123
 124
 125 static struct clk clkout1_clk = {
 126         .name = "clkout1",
 127         .parent = &pll1_aux_clk,
 128         /* NOTE:  clkout1 can be externally gated by muxing GPIO-18 */
 129 };
 130
 131 static struct clk clkout2_clk = {
 132         .name = "clkout2",
 133         .parent = &pll1_sysclkbp,
 134 };
 135
 136 static struct clk pll2_clk = {
 137         .name = "pll2",
 138         .parent = &ref_clk,
 139         .flags = CLK_PLL,
 140         .pll_data = &pll2_data,
 141 };
 142
 143 static struct clk pll2_sysclk1 = {
 144         .name = "pll2_sysclk1",
 145         .parent = &pll2_clk,
 146         .flags = CLK_PLL,
 147         .div_reg = PLLDIV1,
 148 };
 149
 150 static struct clk pll2_sysclkbp = {
 151         .name = "pll2_sysclkbp",
 152         .parent = &pll2_clk,
 153         .flags = CLK_PLL | PRE_PLL,
 154         .div_reg = BPDIV
 155 };
 156
 157 static struct clk clkout3_clk = {
 158         .name = "clkout3",
 159         .parent = &pll2_sysclkbp,
 160         /* NOTE:  clkout3 can be externally gated by muxing GPIO-16 */
 161 };
 162
 163 static struct clk arm_clk = {
 164         .name = "arm_clk",
 165         .parent = &pll1_sysclk1,
 166         .lpsc = DAVINCI_LPSC_ARM,
 167         .flags = ALWAYS_ENABLED,
 168 };
 169
 170 /*
 171  * NOT LISTED below, and not touched by Linux
 172  *   - in SyncReset state by default
 173  *      .lpsc = DAVINCI_LPSC_TPCC,
 174  *      .lpsc = DAVINCI_LPSC_TPTC0,
 175  *      .lpsc = DAVINCI_LPSC_TPTC1,
 176  *      .lpsc = DAVINCI_LPSC_DDR_EMIF, .parent = &sysclk2_clk,
 177  *      .lpsc = DAVINCI_LPSC_MEMSTICK,
 178  *   - in Enabled state by default
 179  *      .lpsc = DAVINCI_LPSC_SYSTEM_SUBSYS,
 180  *      .lpsc = DAVINCI_LPSC_SCR2,      // "bus"
 181  *      .lpsc = DAVINCI_LPSC_SCR3,      // "bus"
 182  *      .lpsc = DAVINCI_LPSC_SCR4,      // "bus"
 183  *      .lpsc = DAVINCI_LPSC_CROSSBAR,  // "emulation"
 184  *      .lpsc = DAVINCI_LPSC_CFG27,     // "test"
 185  *      .lpsc = DAVINCI_LPSC_CFG3,      // "test"
 186  *      .lpsc = DAVINCI_LPSC_CFG5,      // "test"
 187  */
 188
 189 static struct clk mjcp_clk = {
 190         .name = "mjcp",
 191         .parent = &pll1_sysclk1,
 192         .lpsc = DAVINCI_LPSC_IMCOP,
 193 };
 194
 195 static struct clk uart0_clk = {
 196         .name = "uart0",
 197         .parent = &pll1_aux_clk,
 198         .lpsc = DAVINCI_LPSC_UART0,
 199 };
 200
 201 static struct clk uart1_clk = {
 202         .name = "uart1",
 203         .parent = &pll1_aux_clk,
 204         .lpsc = DAVINCI_LPSC_UART1,
 205 };
 206
 207 static struct clk uart2_clk = {
 208         .name = "uart2",
 209         .parent = &pll1_sysclk2,
 210         .lpsc = DAVINCI_LPSC_UART2,
 211 };
 212
 213 static struct clk i2c_clk = {
 214         .name = "i2c",
 215         .parent = &pll1_aux_clk,
 216         .lpsc = DAVINCI_LPSC_I2C,
 217 };
 218
 219 static struct clk asp0_clk = {
 220         .name = "asp0",
 221         .parent = &pll1_sysclk2,
 222         .lpsc = DAVINCI_LPSC_McBSP,
 223 };
 224
 225 static struct clk asp1_clk = {
 226         .name = "asp1",
 227         .parent = &pll1_sysclk2,
 228         .lpsc = DM355_LPSC_McBSP1,
 229 };
 230
 231 static struct clk mmcsd0_clk = {
 232         .name = "mmcsd0",
 233         .parent = &pll1_sysclk2,
 234         .lpsc = DAVINCI_LPSC_MMC_SD,
 235 };
 236
 237 static struct clk mmcsd1_clk = {
 238         .name = "mmcsd1",
 239         .parent = &pll1_sysclk2,
 240         .lpsc = DM355_LPSC_MMC_SD1,
 241 };
 242
 243 static struct clk spi0_clk = {
 244         .name = "spi0",
 245         .parent = &pll1_sysclk2,
 246         .lpsc = DAVINCI_LPSC_SPI,
 247 };
 248
 249 static struct clk spi1_clk = {
 250         .name = "spi1",
 251         .parent = &pll1_sysclk2,
 252         .lpsc = DM355_LPSC_SPI1,
 253 };
 254
 255 static struct clk spi2_clk = {
 256         .name = "spi2",
 257         .parent = &pll1_sysclk2,
 258         .lpsc = DM355_LPSC_SPI2,
 259 };
 260
 261 static struct clk gpio_clk = {
 262         .name = "gpio",
 263         .parent = &pll1_sysclk2,
 264         .lpsc = DAVINCI_LPSC_GPIO,
 265 };
 266
 267 static struct clk aemif_clk = {
 268         .name = "aemif",
 269         .parent = &pll1_sysclk2,
 270         .lpsc = DAVINCI_LPSC_AEMIF,
 271 };
 272
 273 static struct clk pwm0_clk = {
 274         .name = "pwm0",
 275         .parent = &pll1_aux_clk,
 276         .lpsc = DAVINCI_LPSC_PWM0,
 277 };
 278
 279 static struct clk pwm1_clk = {
 280         .name = "pwm1",
 281         .parent = &pll1_aux_clk,
 282         .lpsc = DAVINCI_LPSC_PWM1,
 283 };
 284
 285 static struct clk pwm2_clk = {
 286         .name = "pwm2",
 287         .parent = &pll1_aux_clk,
 288         .lpsc = DAVINCI_LPSC_PWM2,
 289 };
 290
 291 static struct clk pwm3_clk = {
 292         .name = "pwm3",
 293         .parent = &pll1_aux_clk,
 294         .lpsc = DM355_LPSC_PWM3,
 295 };
 296
 297 static struct clk timer0_clk = {
 298         .name = "timer0",
 299         .parent = &pll1_aux_clk,
 300         .lpsc = DAVINCI_LPSC_TIMER0,
 301 };
 302
 303 static struct clk timer1_clk = {
 304         .name = "timer1",
 305         .parent = &pll1_aux_clk,
 306         .lpsc = DAVINCI_LPSC_TIMER1,
 307 };
 308
 309 static struct clk timer2_clk = {
 310         .name = "timer2",
 311         .parent = &pll1_aux_clk,
 312         .lpsc = DAVINCI_LPSC_TIMER2,
 313         .usecount = 1,              /* REVISIT: why cant' this be disabled? */
 314 };
 315
 316 static struct clk timer3_clk = {
 317         .name = "timer3",
 318         .parent = &pll1_aux_clk,
 319         .lpsc = DM355_LPSC_TIMER3,
 320 };
 321
 322 static struct clk rto_clk = {
 323         .name = "rto",
 324         .parent = &pll1_aux_clk,
 325         .lpsc = DM355_LPSC_RTO,
 326 };
 327
 328 static struct clk usb_clk = {
 329         .name = "usb",
 330         .parent = &pll1_sysclk2,
 331         .lpsc = DAVINCI_LPSC_USB,
 332 };
 333
 334 static struct davinci_clk dm355_clks[] = {
 335         CLK(NULL, "ref", &ref_clk),
 336         CLK(NULL, "pll1", &pll1_clk),
 337         CLK(NULL, "pll1_sysclk1", &pll1_sysclk1),
 338         CLK(NULL, "pll1_sysclk2", &pll1_sysclk2),
 339         CLK(NULL, "pll1_sysclk3", &pll1_sysclk3),
 340         CLK(NULL, "pll1_sysclk4", &pll1_sysclk4),
 341         CLK(NULL, "pll1_aux", &pll1_aux_clk),
 342         CLK(NULL, "pll1_sysclkbp", &pll1_sysclkbp),
 343         CLK(NULL, "vpss_dac", &vpss_dac_clk),
 344         CLK(NULL, "vpss_master", &vpss_master_clk),
 345         CLK(NULL, "vpss_slave", &vpss_slave_clk),
 346         CLK(NULL, "clkout1", &clkout1_clk),
 347         CLK(NULL, "clkout2", &clkout2_clk),
 348         CLK(NULL, "pll2", &pll2_clk),
 349         CLK(NULL, "pll2_sysclk1", &pll2_sysclk1),
 350         CLK(NULL, "pll2_sysclkbp", &pll2_sysclkbp),
 351         CLK(NULL, "clkout3", &clkout3_clk),
 352         CLK(NULL, "arm", &arm_clk),
 353         CLK(NULL, "mjcp", &mjcp_clk),
 354         CLK(NULL, "uart0", &uart0_clk),
 355         CLK(NULL, "uart1", &uart1_clk),
 356         CLK(NULL, "uart2", &uart2_clk),
 357         CLK("i2c_davinci.1", NULL, &i2c_clk),
 358         CLK("soc-audio.0", NULL, &asp0_clk),
 359         CLK("soc-audio.1", NULL, &asp1_clk),
 360         CLK("davinci_mmc.0", NULL, &mmcsd0_clk),
 361         CLK("davinci_mmc.1", NULL, &mmcsd1_clk),
 362         CLK(NULL, "spi0", &spi0_clk),
 363         CLK(NULL, "spi1", &spi1_clk),
 364         CLK(NULL, "spi2", &spi2_clk),
 365         CLK(NULL, "gpio", &gpio_clk),
 366         CLK(NULL, "aemif", &aemif_clk),
 367         CLK(NULL, "pwm0", &pwm0_clk),
 368         CLK(NULL, "pwm1", &pwm1_clk),
 369         CLK(NULL, "pwm2", &pwm2_clk),
 370         CLK(NULL, "pwm3", &pwm3_clk),
 371         CLK(NULL, "timer0", &timer0_clk),
 372         CLK(NULL, "timer1", &timer1_clk),
 373         CLK("watchdog", NULL, &timer2_clk),
 374         CLK(NULL, "timer3", &timer3_clk),
 375         CLK(NULL, "rto", &rto_clk),
 376         CLK(NULL, "usb", &usb_clk),
 377         CLK(NULL, NULL, NULL),
 378 };
 379
 380 /*----------------------------------------------------------------------*/
 381
 382 static u64 dm355_spi0_dma_mask = DMA_BIT_MASK(32);
 383
 384 static struct resource dm355_spi0_resources[] = {
 385         {
 386                 .start = 0x01c66000,
 387                 .end   = 0x01c667ff,
 388                 .flags = IORESOURCE_MEM,
 389         },
 390         {
 391                 .start = IRQ_DM355_SPINT0_1,
 392                 .flags = IORESOURCE_IRQ,
 393         },
 394         /* Not yet used, so not included:
 395          * IORESOURCE_IRQ:
 396          *  - IRQ_DM355_SPINT0_0
 397          * IORESOURCE_DMA:
 398          *  - DAVINCI_DMA_SPI_SPIX
 399          *  - DAVINCI_DMA_SPI_SPIR
 400          */
 401 };
 402
 403 static struct platform_device dm355_spi0_device = {
 404         .name = "spi_davinci",
 405         .id = 0,
 406         .dev = {
 407                 .dma_mask = &dm355_spi0_dma_mask,
 408                 .coherent_dma_mask = DMA_BIT_MASK(32),
 409         },
 410         .num_resources = ARRAY_SIZE(dm355_spi0_resources),
 411         .resource = dm355_spi0_resources,
 412 };
 413
 414 void __init dm355_init_spi0(unsigned chipselect_mask,
 415                 struct spi_board_info *info, unsigned len)
 416 {
 417         /* for now, assume we need MISO */
 418         davinci_cfg_reg(DM355_SPI0_SDI);
 419
 420         /* not all slaves will be wired up */
 421         if (chipselect_mask & BIT(0))
 422                 davinci_cfg_reg(DM355_SPI0_SDENA0);
 423         if (chipselect_mask & BIT(1))
 424                 davinci_cfg_reg(DM355_SPI0_SDENA1);
 425
 426         spi_register_board_info(info, len);
 427
 428         platform_device_register(&dm355_spi0_device);
 429 }
 430
 431 /*----------------------------------------------------------------------*/
 432
 433 /*
 434  * Device specific mux setup
 435  *
 436  *      soc     description     mux  mode   mode  mux    dbg
 437  *                              reg  offset mask  mode
 438  */
 439 static const struct mux_config dm355_pins[] = {
 440 #ifdef CONFIG_DAVINCI_MUX
 441 MUX_CFG(DM355,  MMCSD0,         4,   2,     1,    0,     false)
 442
 443 MUX_CFG(DM355,  SD1_CLK,        3,   6,     1,    1,     false)
 444 MUX_CFG(DM355,  SD1_CMD,        3,   7,     1,    1,     false)
 445 MUX_CFG(DM355,  SD1_DATA3,      3,   8,     3,    1,     false)
 446 MUX_CFG(DM355,  SD1_DATA2,      3,   10,    3,    1,     false)
 447 MUX_CFG(DM355,  SD1_DATA1,      3,   12,    3,    1,     false)
 448 MUX_CFG(DM355,  SD1_DATA0,      3,   14,    3,    1,     false)
 449
 450 MUX_CFG(DM355,  I2C_SDA,        3,   19,    1,    1,     false)
 451 MUX_CFG(DM355,  I2C_SCL,        3,   20,    1,    1,     false)
 452
 453 MUX_CFG(DM355,  MCBSP0_BDX,     3,   0,     1,    1,     false)
 454 MUX_CFG(DM355,  MCBSP0_X,       3,   1,     1,    1,     false)
 455 MUX_CFG(DM355,  MCBSP0_BFSX,    3,   2,     1,    1,     false)
 456 MUX_CFG(DM355,  MCBSP0_BDR,     3,   3,     1,    1,     false)
 457 MUX_CFG(DM355,  MCBSP0_R,       3,   4,     1,    1,     false)
 458 MUX_CFG(DM355,  MCBSP0_BFSR,    3,   5,     1,    1,     false)
 459
 460 MUX_CFG(DM355,  SPI0_SDI,       4,   1,     1,    0,     false)
 461 MUX_CFG(DM355,  SPI0_SDENA0,    4,   0,     1,    0,     false)
 462 MUX_CFG(DM355,  SPI0_SDENA1,    3,   28,    1,    1,     false)
 463
 464 INT_CFG(DM355,  INT_EDMA_CC,          2,    1,    1,     false)
 465 INT_CFG(DM355,  INT_EDMA_TC0_ERR,     3,    1,    1,     false)
 466 INT_CFG(DM355,  INT_EDMA_TC1_ERR,     4,    1,    1,     false)
 467
 468 EVT_CFG(DM355,  EVT8_ASP1_TX,         0,    1,    0,     false)
 469 EVT_CFG(DM355,  EVT9_ASP1_RX,         1,    1,    0,     false)
 470 EVT_CFG(DM355,  EVT26_MMC0_RX,        2,    1,    0,     false)
 471 #endif
 472 };
 473
 474 static u8 dm355_default_priorities[DAVINCI_N_AINTC_IRQ] = {
 475         [IRQ_DM355_CCDC_VDINT0]         = 2,
 476         [IRQ_DM355_CCDC_VDINT1]         = 6,
 477         [IRQ_DM355_CCDC_VDINT2]         = 6,
 478         [IRQ_DM355_IPIPE_HST]           = 6,
 479         [IRQ_DM355_H3AINT]              = 6,
 480         [IRQ_DM355_IPIPE_SDR]           = 6,
 481         [IRQ_DM355_IPIPEIFINT]          = 6,
 482         [IRQ_DM355_OSDINT]              = 7,
 483         [IRQ_DM355_VENCINT]             = 6,
 484         [IRQ_ASQINT]                    = 6,
 485         [IRQ_IMXINT]                    = 6,
 486         [IRQ_USBINT]                    = 4,
 487         [IRQ_DM355_RTOINT]              = 4,
 488         [IRQ_DM355_UARTINT2]            = 7,
 489         [IRQ_DM355_TINT6]               = 7,
 490         [IRQ_CCINT0]                    = 5,    /* dma */
 491         [IRQ_CCERRINT]                  = 5,    /* dma */
 492         [IRQ_TCERRINT0]                 = 5,    /* dma */
 493         [IRQ_TCERRINT]                  = 5,    /* dma */
 494         [IRQ_DM355_SPINT2_1]            = 7,
 495         [IRQ_DM355_TINT7]               = 4,
 496         [IRQ_DM355_SDIOINT0]            = 7,
 497         [IRQ_MBXINT]                    = 7,
 498         [IRQ_MBRINT]                    = 7,
 499         [IRQ_MMCINT]                    = 7,
 500         [IRQ_DM355_MMCINT1]             = 7,
 501         [IRQ_DM355_PWMINT3]             = 7,
 502         [IRQ_DDRINT]                    = 7,
 503         [IRQ_AEMIFINT]                  = 7,
 504         [IRQ_DM355_SDIOINT1]            = 4,
 505         [IRQ_TINT0_TINT12]              = 2,    /* clockevent */
 506         [IRQ_TINT0_TINT34]              = 2,    /* clocksource */
 507         [IRQ_TINT1_TINT12]              = 7,    /* DSP timer */
 508         [IRQ_TINT1_TINT34]              = 7,    /* system tick */
 509         [IRQ_PWMINT0]                   = 7,
 510         [IRQ_PWMINT1]                   = 7,
 511         [IRQ_PWMINT2]                   = 7,
 512         [IRQ_I2C]                       = 3,
 513         [IRQ_UARTINT0]                  = 3,
 514         [IRQ_UARTINT1]                  = 3,
 515         [IRQ_DM355_SPINT0_0]            = 3,
 516         [IRQ_DM355_SPINT0_1]            = 3,
 517         [IRQ_DM355_GPIO0]               = 3,
 518         [IRQ_DM355_GPIO1]               = 7,
 519         [IRQ_DM355_GPIO2]               = 4,
 520         [IRQ_DM355_GPIO3]               = 4,
 521         [IRQ_DM355_GPIO4]               = 7,
 522         [IRQ_DM355_GPIO5]               = 7,
 523         [IRQ_DM355_GPIO6]               = 7,
 524         [IRQ_DM355_GPIO7]               = 7,
 525         [IRQ_DM355_GPIO8]               = 7,
 526         [IRQ_DM355_GPIO9]               = 7,
 527         [IRQ_DM355_GPIOBNK0]            = 7,
 528         [IRQ_DM355_GPIOBNK1]            = 7,
 529         [IRQ_DM355_GPIOBNK2]            = 7,
 530         [IRQ_DM355_GPIOBNK3]            = 7,
 531         [IRQ_DM355_GPIOBNK4]            = 7,
 532         [IRQ_DM355_GPIOBNK5]            = 7,
 533         [IRQ_DM355_GPIOBNK6]            = 7,
 534         [IRQ_COMMTX]                    = 7,
 535         [IRQ_COMMRX]                    = 7,
 536         [IRQ_EMUINT]                    = 7,
 537 };
 538
 539 /*----------------------------------------------------------------------*/
 540
 541 static const s8 dma_chan_dm355_no_event[] = {
 542         12, 13, 24, 56, 57,
 543         58, 59, 60, 61, 62,
 544         63,
 545         -1
 546 };
 547
 548 static struct edma_soc_info dm355_edma_info = {
 549         .n_channel      = 64,
 550         .n_region       = 4,
 551         .n_slot         = 128,
 552         .n_tc           = 2,
 553         .noevent        = dma_chan_dm355_no_event,
 554 };
 555
 556 static struct resource edma_resources[] = {
 557         {
 558                 .name   = "edma_cc",
 559                 .start  = 0x01c00000,
 560                 .end    = 0x01c00000 + SZ_64K - 1,
 561                 .flags  = IORESOURCE_MEM,
 562         },
 563         {
 564                 .name   = "edma_tc0",
 565                 .start  = 0x01c10000,
 566                 .end    = 0x01c10000 + SZ_1K - 1,
 567                 .flags  = IORESOURCE_MEM,
 568         },
 569         {
 570                 .name   = "edma_tc1",
 571                 .start  = 0x01c10400,
 572                 .end    = 0x01c10400 + SZ_1K - 1,
 573                 .flags  = IORESOURCE_MEM,
 574         },
 575         {
 576                 .start  = IRQ_CCINT0,
 577                 .flags  = IORESOURCE_IRQ,
 578         },
 579         {
 580                 .start  = IRQ_CCERRINT,
 581                 .flags  = IORESOURCE_IRQ,
 582         },
 583         /* not using (or muxing) TC*_ERR */
 584 };
 585
 586 static struct platform_device dm355_edma_device = {
 587         .name                   = "edma",
 588         .id                     = -1,
 589         .dev.platform_data      = &dm355_edma_info,
 590         .num_resources          = ARRAY_SIZE(edma_resources),
 591         .resource               = edma_resources,
 592 };
 593
 594 /*----------------------------------------------------------------------*/
 595
 596 static struct map_desc dm355_io_desc[] = {
 597         {
 598                 .virtual        = IO_VIRT,
 599                 .pfn            = __phys_to_pfn(IO_PHYS),
 600                 .length         = IO_SIZE,
 601                 .type           = MT_DEVICE
 602         },
 603 };
 604
 605 /* Contents of JTAG ID register used to identify exact cpu type */
 606 static struct davinci_id dm355_ids[] = {
 607         {
 608                 .variant        = 0x0,
 609                 .part_no        = 0xb73b,
 610                 .manufacturer   = 0x00f,
 611                 .cpu_id         = DAVINCI_CPU_ID_DM355,
 612                 .name           = "dm355",
 613         },
 614 };
 615
 616 static void __iomem *dm355_psc_bases[] = {
 617         IO_ADDRESS(DAVINCI_PWR_SLEEP_CNTRL_BASE),
 618 };
 619
 620 /*
 621  * T0_BOT: Timer 0, bottom:  clockevent source for hrtimers
 622  * T0_TOP: Timer 0, top   :  clocksource for generic timekeeping
 623  * T1_BOT: Timer 1, bottom:  (used by DSP in TI DSPLink code)
 624  * T1_TOP: Timer 1, top   :  <unused>
 625  */
 626 struct davinci_timer_info dm355_timer_info = {
 627         .timers         = davinci_timer_instance,
 628         .clockevent_id  = T0_BOT,
 629         .clocksource_id = T0_TOP,
 630 };
 631
 632 static struct davinci_soc_info davinci_soc_info_dm355 = {
 633         .io_desc                = dm355_io_desc,
 634         .io_desc_num            = ARRAY_SIZE(dm355_io_desc),
 635         .jtag_id_base           = IO_ADDRESS(0x01c40028),
 636         .ids                    = dm355_ids,
 637         .ids_num                = ARRAY_SIZE(dm355_ids),
 638         .cpu_clks               = dm355_clks,
 639         .psc_bases              = dm355_psc_bases,
 640         .psc_bases_num          = ARRAY_SIZE(dm355_psc_bases),
 641         .pinmux_base            = IO_ADDRESS(DAVINCI_SYSTEM_MODULE_BASE),
 642         .pinmux_pins            = dm355_pins,
 643         .pinmux_pins_num        = ARRAY_SIZE(dm355_pins),
 644         .intc_base              = IO_ADDRESS(DAVINCI_ARM_INTC_BASE),
 645         .intc_type              = DAVINCI_INTC_TYPE_AINTC,
 646         .intc_irq_prios         = dm355_default_priorities,
 647         .intc_irq_num           = DAVINCI_N_AINTC_IRQ,
 648         .timer_info             = &dm355_timer_info,
 649 };
 650
 651 void __init dm355_init(void)
 652 {
 653         davinci_common_init(&davinci_soc_info_dm355);
 654 }
 655
 656 static int __init dm355_init_devices(void)
 657 {
 658         if (!cpu_is_davinci_dm355())
 659                 return 0;
 660
 661         davinci_cfg_reg(DM355_INT_EDMA_CC);
 662         platform_device_register(&dm355_edma_device);
 663         return 0;
 664 }
 665 postcore_initcall(dm355_init_devices);