2 * Clock and PLL control for DaVinci devices
4 * Copyright (C) 2006-2007 Texas Instruments.
5 * Copyright (C) 2008-2009 Deep Root Systems, LLC
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/clk.h>
18 #include <linux/err.h>
19 #include <linux/mutex.h>
20 #include <linux/platform_device.h>
23 #include <mach/hardware.h>
26 #include <mach/cputype.h>
29 static LIST_HEAD(clocks);
30 static DEFINE_MUTEX(clocks_mutex);
31 static DEFINE_SPINLOCK(clockfw_lock);
33 static unsigned psc_domain(struct clk *clk)
35 return (clk->flags & PSC_DSP)
36 ? DAVINCI_GPSC_DSPDOMAIN
37 : DAVINCI_GPSC_ARMDOMAIN;
40 static void __clk_enable(struct clk *clk)
43 __clk_enable(clk->parent);
44 if (clk->usecount++ == 0 && (clk->flags & CLK_PSC))
45 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
49 static void __clk_disable(struct clk *clk)
51 if (WARN_ON(clk->usecount == 0))
53 if (--clk->usecount == 0 && !(clk->flags & CLK_PLL))
54 davinci_psc_config(psc_domain(clk), clk->psc_ctlr,
57 __clk_disable(clk->parent);
60 int clk_enable(struct clk *clk)
64 if (clk == NULL || IS_ERR(clk))
67 spin_lock_irqsave(&clockfw_lock, flags);
69 spin_unlock_irqrestore(&clockfw_lock, flags);
73 EXPORT_SYMBOL(clk_enable);
75 void clk_disable(struct clk *clk)
79 if (clk == NULL || IS_ERR(clk))
82 spin_lock_irqsave(&clockfw_lock, flags);
84 spin_unlock_irqrestore(&clockfw_lock, flags);
86 EXPORT_SYMBOL(clk_disable);
88 unsigned long clk_get_rate(struct clk *clk)
90 if (clk == NULL || IS_ERR(clk))
95 EXPORT_SYMBOL(clk_get_rate);
97 long clk_round_rate(struct clk *clk, unsigned long rate)
99 if (clk == NULL || IS_ERR(clk))
104 EXPORT_SYMBOL(clk_round_rate);
106 int clk_set_rate(struct clk *clk, unsigned long rate)
108 if (clk == NULL || IS_ERR(clk))
111 /* changing the clk rate is not supported */
114 EXPORT_SYMBOL(clk_set_rate);
116 int clk_register(struct clk *clk)
118 if (clk == NULL || IS_ERR(clk))
121 if (WARN(clk->parent && !clk->parent->rate,
122 "CLK: %s parent %s has no rate!\n",
123 clk->name, clk->parent->name))
126 INIT_LIST_HEAD(&clk->children);
128 mutex_lock(&clocks_mutex);
129 list_add_tail(&clk->node, &clocks);
131 list_add_tail(&clk->childnode, &clk->parent->children);
132 mutex_unlock(&clocks_mutex);
134 /* If rate is already set, use it */
138 /* Otherwise, default to parent rate */
140 clk->rate = clk->parent->rate;
144 EXPORT_SYMBOL(clk_register);
146 void clk_unregister(struct clk *clk)
148 if (clk == NULL || IS_ERR(clk))
151 mutex_lock(&clocks_mutex);
152 list_del(&clk->node);
153 list_del(&clk->childnode);
154 mutex_unlock(&clocks_mutex);
156 EXPORT_SYMBOL(clk_unregister);
158 #ifdef CONFIG_DAVINCI_RESET_CLOCKS
160 * Disable any unused clocks left on by the bootloader
162 static int __init clk_disable_unused(void)
166 spin_lock_irq(&clockfw_lock);
167 list_for_each_entry(ck, &clocks, node) {
168 if (ck->usecount > 0)
170 if (!(ck->flags & CLK_PSC))
173 /* ignore if in Disabled or SwRstDisable states */
174 if (!davinci_psc_is_clk_active(ck->psc_ctlr, ck->lpsc))
177 pr_info("Clocks: disable unused %s\n", ck->name);
178 davinci_psc_config(psc_domain(ck), ck->psc_ctlr, ck->lpsc, 0);
180 spin_unlock_irq(&clockfw_lock);
184 late_initcall(clk_disable_unused);
187 static void clk_sysclk_recalc(struct clk *clk)
190 struct pll_data *pll;
192 /* If this is the PLL base clock, no more calculations needed */
196 if (WARN_ON(!clk->parent))
199 clk->rate = clk->parent->rate;
201 /* Otherwise, the parent must be a PLL */
202 if (WARN_ON(!clk->parent->pll_data))
205 pll = clk->parent->pll_data;
207 /* If pre-PLL, source clock is before the multiplier and divider(s) */
208 if (clk->flags & PRE_PLL)
209 clk->rate = pll->input_rate;
214 v = __raw_readl(pll->base + clk->div_reg);
216 plldiv = (v & PLLDIV_RATIO_MASK) + 1;
222 static void __init clk_pll_init(struct clk *clk)
224 u32 ctrl, mult = 1, prediv = 1, postdiv = 1;
226 struct pll_data *pll = clk->pll_data;
228 pll->base = IO_ADDRESS(pll->phys_base);
229 ctrl = __raw_readl(pll->base + PLLCTL);
230 clk->rate = pll->input_rate = clk->parent->rate;
232 if (ctrl & PLLCTL_PLLEN) {
234 mult = __raw_readl(pll->base + PLLM);
235 if (cpu_is_davinci_dm365())
236 mult = 2 * (mult & PLLM_PLLM_MASK);
238 mult = (mult & PLLM_PLLM_MASK) + 1;
242 if (pll->flags & PLL_HAS_PREDIV) {
243 prediv = __raw_readl(pll->base + PREDIV);
244 if (prediv & PLLDIV_EN)
245 prediv = (prediv & PLLDIV_RATIO_MASK) + 1;
250 /* pre-divider is fixed, but (some?) chips won't report that */
251 if (cpu_is_davinci_dm355() && pll->num == 1)
254 if (pll->flags & PLL_HAS_POSTDIV) {
255 postdiv = __raw_readl(pll->base + POSTDIV);
256 if (postdiv & PLLDIV_EN)
257 postdiv = (postdiv & PLLDIV_RATIO_MASK) + 1;
265 clk->rate /= postdiv;
268 pr_debug("PLL%d: input = %lu MHz [ ",
269 pll->num, clk->parent->rate / 1000000);
273 pr_debug("/ %d ", prediv);
275 pr_debug("* %d ", mult);
277 pr_debug("/ %d ", postdiv);
278 pr_debug("] --> %lu MHz output.\n", clk->rate / 1000000);
281 int __init davinci_clk_init(struct davinci_clk *clocks)
283 struct davinci_clk *c;
286 for (c = clocks; c->lk.clk; c++) {
292 /* Calculate rates for PLL-derived clocks */
293 else if (clk->flags & CLK_PLL)
294 clk_sysclk_recalc(clk);
297 clk->flags |= CLK_PSC;
302 /* Turn on clocks that Linux doesn't otherwise manage */
303 if (clk->flags & ALWAYS_ENABLED)
310 #ifdef CONFIG_PROC_FS
311 #include <linux/proc_fs.h>
312 #include <linux/seq_file.h>
314 static void *davinci_ck_start(struct seq_file *m, loff_t *pos)
316 return *pos < 1 ? (void *)1 : NULL;
319 static void *davinci_ck_next(struct seq_file *m, void *v, loff_t *pos)
325 static void davinci_ck_stop(struct seq_file *m, void *v)
329 #define CLKNAME_MAX 10 /* longest clock name */
334 dump_clock(struct seq_file *s, unsigned nest, struct clk *parent)
337 char buf[CLKNAME_MAX + NEST_DELTA * NEST_MAX];
341 if (parent->flags & CLK_PLL)
343 else if (parent->flags & CLK_PSC)
348 /* <nest spaces> name <pad to end> */
349 memset(buf, ' ', sizeof(buf) - 1);
350 buf[sizeof(buf) - 1] = 0;
351 i = strlen(parent->name);
352 memcpy(buf + nest, parent->name,
353 min(i, (unsigned)(sizeof(buf) - 1 - nest)));
355 seq_printf(s, "%s users=%2d %-3s %9ld Hz\n",
356 buf, parent->usecount, state, clk_get_rate(parent));
357 /* REVISIT show device associations too */
359 /* cost is now small, but not linear... */
360 list_for_each_entry(clk, &parent->children, childnode) {
361 dump_clock(s, nest + NEST_DELTA, clk);
365 static int davinci_ck_show(struct seq_file *m, void *v)
367 /* Show clock tree; we know the main oscillator is first.
368 * We trust nonzero usecounts equate to PSC enables...
370 mutex_lock(&clocks_mutex);
371 if (!list_empty(&clocks))
372 dump_clock(m, 0, list_first_entry(&clocks, struct clk, node));
373 mutex_unlock(&clocks_mutex);
378 static const struct seq_operations davinci_ck_op = {
379 .start = davinci_ck_start,
380 .next = davinci_ck_next,
381 .stop = davinci_ck_stop,
382 .show = davinci_ck_show
385 static int davinci_ck_open(struct inode *inode, struct file *file)
387 return seq_open(file, &davinci_ck_op);
390 static const struct file_operations proc_davinci_ck_operations = {
391 .open = davinci_ck_open,
394 .release = seq_release,
397 static int __init davinci_ck_proc_init(void)
399 proc_create("davinci_clocks", 0, NULL, &proc_davinci_ck_operations);
403 __initcall(davinci_ck_proc_init);
404 #endif /* CONFIG_DEBUG_PROC_FS */