2 * TI DaVinci EVM board support
4 * Author: Kevin Hilman, MontaVista Software, Inc. <source@mvista.com>
6 * 2007 (c) MontaVista Software, Inc. This file is licensed under
7 * the terms of the GNU General Public License version 2. This program
8 * is licensed "as is" without any warranty of any kind, whether express
11 #include <linux/kernel.h>
12 #include <linux/module.h>
13 #include <linux/init.h>
14 #include <linux/dma-mapping.h>
15 #include <linux/platform_device.h>
16 #include <linux/gpio.h>
17 #include <linux/leds.h>
18 #include <linux/memory.h>
20 #include <linux/i2c.h>
21 #include <linux/i2c/pcf857x.h>
22 #include <linux/i2c/at24.h>
23 #include <linux/etherdevice.h>
24 #include <linux/mtd/mtd.h>
25 #include <linux/mtd/nand.h>
26 #include <linux/mtd/partitions.h>
27 #include <linux/mtd/physmap.h>
29 #include <linux/phy.h>
30 #include <linux/clk.h>
32 #include <asm/setup.h>
33 #include <asm/mach-types.h>
35 #include <asm/mach/arch.h>
36 #include <asm/mach/map.h>
37 #include <asm/mach/flash.h>
39 #include <mach/dm644x.h>
40 #include <mach/common.h>
42 #include <mach/serial.h>
45 #include <mach/nand.h>
47 #include <mach/emac.h>
49 #define DM644X_EVM_PHY_MASK (0x2)
50 #define DM644X_EVM_MDIO_FREQUENCY (2200000) /* PHY bus frequency */
52 #define DAVINCI_CFC_ATA_BASE 0x01C66000
54 #define DAVINCI_ASYNC_EMIF_CONTROL_BASE 0x01e00000
55 #define DAVINCI_ASYNC_EMIF_DATA_CE0_BASE 0x02000000
56 #define DAVINCI_ASYNC_EMIF_DATA_CE1_BASE 0x04000000
57 #define DAVINCI_ASYNC_EMIF_DATA_CE2_BASE 0x06000000
58 #define DAVINCI_ASYNC_EMIF_DATA_CE3_BASE 0x08000000
60 #define LXT971_PHY_ID (0x001378e2)
61 #define LXT971_PHY_MASK (0xfffffff0)
63 static struct mtd_partition davinci_evm_norflash_partitions[] = {
64 /* bootloader (UBL, U-Boot, etc) in first 5 sectors */
69 .mask_flags = MTD_WRITEABLE, /* force read-only */
71 /* bootloader params in the next 1 sectors */
74 .offset = MTDPART_OFS_APPEND,
81 .offset = MTDPART_OFS_APPEND,
88 .offset = MTDPART_OFS_APPEND,
89 .size = MTDPART_SIZ_FULL,
94 static struct physmap_flash_data davinci_evm_norflash_data = {
96 .parts = davinci_evm_norflash_partitions,
97 .nr_parts = ARRAY_SIZE(davinci_evm_norflash_partitions),
100 /* NOTE: CFI probe will correctly detect flash part as 32M, but EMIF
101 * limits addresses to 16M, so using addresses past 16M will wrap */
102 static struct resource davinci_evm_norflash_resource = {
103 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
104 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
105 .flags = IORESOURCE_MEM,
108 static struct platform_device davinci_evm_norflash_device = {
109 .name = "physmap-flash",
112 .platform_data = &davinci_evm_norflash_data,
115 .resource = &davinci_evm_norflash_resource,
118 /* DM644x EVM includes a 64 MByte small-page NAND flash (16K blocks).
119 * It may used instead of the (default) NOR chip to boot, using TI's
120 * tools to install the secondary boot loader (UBL) and U-Boot.
122 struct mtd_partition davinci_evm_nandflash_partition[] = {
123 /* Bootloader layout depends on whose u-boot is installed, but we
124 * can hide all the details.
125 * - block 0 for u-boot environment ... in mainline u-boot
126 * - block 1 for UBL (plus up to four backup copies in blocks 2..5)
127 * - blocks 6...? for u-boot
128 * - blocks 16..23 for u-boot environment ... in TI's u-boot
131 .name = "bootloader",
133 .size = SZ_256K + SZ_128K,
134 .mask_flags = MTD_WRITEABLE, /* force read-only */
139 .offset = MTDPART_OFS_APPEND,
143 /* File system (older GIT kernels started this on the 5MB mark) */
145 .name = "filesystem",
146 .offset = MTDPART_OFS_APPEND,
147 .size = MTDPART_SIZ_FULL,
150 /* A few blocks at end hold a flash BBT ... created by TI's CCS
151 * using flashwriter_nand.out, but ignored by TI's versions of
152 * Linux and u-boot. We boot faster by using them.
156 static struct davinci_nand_pdata davinci_evm_nandflash_data = {
157 .parts = davinci_evm_nandflash_partition,
158 .nr_parts = ARRAY_SIZE(davinci_evm_nandflash_partition),
159 .ecc_mode = NAND_ECC_HW,
160 .options = NAND_USE_FLASH_BBT,
163 static struct resource davinci_evm_nandflash_resource[] = {
165 .start = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE,
166 .end = DAVINCI_ASYNC_EMIF_DATA_CE0_BASE + SZ_16M - 1,
167 .flags = IORESOURCE_MEM,
169 .start = DAVINCI_ASYNC_EMIF_CONTROL_BASE,
170 .end = DAVINCI_ASYNC_EMIF_CONTROL_BASE + SZ_4K - 1,
171 .flags = IORESOURCE_MEM,
175 static struct platform_device davinci_evm_nandflash_device = {
176 .name = "davinci_nand",
179 .platform_data = &davinci_evm_nandflash_data,
181 .num_resources = ARRAY_SIZE(davinci_evm_nandflash_resource),
182 .resource = davinci_evm_nandflash_resource,
185 static u64 davinci_fb_dma_mask = DMA_BIT_MASK(32);
187 static struct platform_device davinci_fb_device = {
191 .dma_mask = &davinci_fb_dma_mask,
192 .coherent_dma_mask = DMA_BIT_MASK(32),
197 static struct platform_device rtc_dev = {
198 .name = "rtc_davinci_evm",
202 static struct resource ide_resources[] = {
204 .start = DAVINCI_CFC_ATA_BASE,
205 .end = DAVINCI_CFC_ATA_BASE + 0x7ff,
206 .flags = IORESOURCE_MEM,
211 .flags = IORESOURCE_IRQ,
215 static u64 ide_dma_mask = DMA_BIT_MASK(32);
217 static struct platform_device ide_dev = {
218 .name = "palm_bk3710",
220 .resource = ide_resources,
221 .num_resources = ARRAY_SIZE(ide_resources),
223 .dma_mask = &ide_dma_mask,
224 .coherent_dma_mask = DMA_BIT_MASK(32),
228 static struct snd_platform_data dm644x_evm_snd_data;
230 /*----------------------------------------------------------------------*/
236 #define PCF_Uxx_BASE(x) (DAVINCI_N_GPIO + ((x) * 8))
241 static struct gpio_led evm_leds[] = {
242 { .name = "DS8", .active_low = 1,
243 .default_trigger = "heartbeat", },
244 { .name = "DS7", .active_low = 1, },
245 { .name = "DS6", .active_low = 1, },
246 { .name = "DS5", .active_low = 1, },
247 { .name = "DS4", .active_low = 1, },
248 { .name = "DS3", .active_low = 1, },
249 { .name = "DS2", .active_low = 1,
250 .default_trigger = "mmc0", },
251 { .name = "DS1", .active_low = 1,
252 .default_trigger = "ide-disk", },
255 static const struct gpio_led_platform_data evm_led_data = {
256 .num_leds = ARRAY_SIZE(evm_leds),
260 static struct platform_device *evm_led_dev;
263 evm_led_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
265 struct gpio_led *leds = evm_leds;
273 /* what an extremely annoying way to be forced to handle
274 * device unregistration ...
276 evm_led_dev = platform_device_alloc("leds-gpio", 0);
277 platform_device_add_data(evm_led_dev,
278 &evm_led_data, sizeof evm_led_data);
280 evm_led_dev->dev.parent = &client->dev;
281 status = platform_device_add(evm_led_dev);
283 platform_device_put(evm_led_dev);
290 evm_led_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
293 platform_device_unregister(evm_led_dev);
299 static struct pcf857x_platform_data pcf_data_u2 = {
300 .gpio_base = PCF_Uxx_BASE(0),
301 .setup = evm_led_setup,
302 .teardown = evm_led_teardown,
306 /* U18 - A/V clock generator and user switch */
311 sw_show(struct device *d, struct device_attribute *a, char *buf)
313 char *s = gpio_get_value_cansleep(sw_gpio) ? "on\n" : "off\n";
319 static DEVICE_ATTR(user_sw, S_IRUGO, sw_show, NULL);
322 evm_u18_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
326 /* export dip switch option */
328 status = gpio_request(sw_gpio, "user_sw");
330 status = gpio_direction_input(sw_gpio);
332 status = device_create_file(&client->dev, &dev_attr_user_sw);
338 /* audio PLL: 48 kHz (vs 44.1 or 32), single rate (vs double) */
339 gpio_request(gpio + 3, "pll_fs2");
340 gpio_direction_output(gpio + 3, 0);
342 gpio_request(gpio + 2, "pll_fs1");
343 gpio_direction_output(gpio + 2, 0);
345 gpio_request(gpio + 1, "pll_sr");
346 gpio_direction_output(gpio + 1, 0);
352 evm_u18_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
359 device_remove_file(&client->dev, &dev_attr_user_sw);
365 static struct pcf857x_platform_data pcf_data_u18 = {
366 .gpio_base = PCF_Uxx_BASE(1),
367 .n_latch = (1 << 3) | (1 << 2) | (1 << 1),
368 .setup = evm_u18_setup,
369 .teardown = evm_u18_teardown,
373 /* U35 - various I/O signals used to manage USB, CF, ATA, etc */
376 evm_u35_setup(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
378 /* p0 = nDRV_VBUS (initial: don't supply it) */
379 gpio_request(gpio + 0, "nDRV_VBUS");
380 gpio_direction_output(gpio + 0, 1);
383 gpio_request(gpio + 1, "VDDIMX_EN");
384 gpio_direction_output(gpio + 1, 1);
387 gpio_request(gpio + 2, "VLYNQ_EN");
388 gpio_direction_output(gpio + 2, 1);
390 /* p3 = n3V3_CF_RESET (initial: stay in reset) */
391 gpio_request(gpio + 3, "nCF_RESET");
392 gpio_direction_output(gpio + 3, 0);
396 /* p5 = 1V8_WLAN_RESET (initial: stay in reset) */
397 gpio_request(gpio + 5, "WLAN_RESET");
398 gpio_direction_output(gpio + 5, 1);
400 /* p6 = nATA_SEL (initial: select) */
401 gpio_request(gpio + 6, "nATA_SEL");
402 gpio_direction_output(gpio + 6, 0);
404 /* p7 = nCF_SEL (initial: deselect) */
405 gpio_request(gpio + 7, "nCF_SEL");
406 gpio_direction_output(gpio + 7, 1);
408 /* irlml6401 switches over 1A, in under 8 msec;
409 * now it can be managed by nDRV_VBUS ...
417 evm_u35_teardown(struct i2c_client *client, int gpio, unsigned ngpio, void *c)
429 static struct pcf857x_platform_data pcf_data_u35 = {
430 .gpio_base = PCF_Uxx_BASE(2),
431 .setup = evm_u35_setup,
432 .teardown = evm_u35_teardown,
435 /*----------------------------------------------------------------------*/
437 /* Most of this EEPROM is unused, but U-Boot uses some data:
438 * - 0x7f00, 6 bytes Ethernet Address
439 * - 0x0039, 1 byte NTSC vs PAL (bit 0x80 == PAL)
440 * - ... newer boards may have more
443 static struct at24_platform_data eeprom_info = {
444 .byte_len = (256*1024) / 8,
446 .flags = AT24_FLAG_ADDR16,
447 .setup = davinci_get_mac_addr,
448 .context = (void *)0x7f00,
452 * MSP430 supports RTC, card detection, input from IR remote, and
453 * a bit more. It triggers interrupts on GPIO(7) from pressing
454 * buttons on the IR remote, and for card detect switches.
456 static struct i2c_client *dm6446evm_msp;
458 static int dm6446evm_msp_probe(struct i2c_client *client,
459 const struct i2c_device_id *id)
461 dm6446evm_msp = client;
465 static int dm6446evm_msp_remove(struct i2c_client *client)
467 dm6446evm_msp = NULL;
471 static const struct i2c_device_id dm6446evm_msp_ids[] = {
472 { "dm6446evm_msp", 0, },
473 { /* end of list */ },
476 static struct i2c_driver dm6446evm_msp_driver = {
477 .driver.name = "dm6446evm_msp",
478 .id_table = dm6446evm_msp_ids,
479 .probe = dm6446evm_msp_probe,
480 .remove = dm6446evm_msp_remove,
483 static int dm6444evm_msp430_get_pins(void)
485 static const char txbuf[2] = { 2, 4, };
487 struct i2c_msg msg[2] = {
489 .addr = dm6446evm_msp->addr,
492 .buf = (void __force *)txbuf,
495 .addr = dm6446evm_msp->addr,
506 /* Command 4 == get input state, returns port 2 and port3 data
507 * S Addr W [A] len=2 [A] cmd=4 [A]
508 * RS Addr R [A] [len=4] A [cmd=4] A [port2] A [port3] N P
510 status = i2c_transfer(dm6446evm_msp->adapter, msg, 2);
514 dev_dbg(&dm6446evm_msp->dev,
515 "PINS: %02x %02x %02x %02x\n",
516 buf[0], buf[1], buf[2], buf[3]);
518 return (buf[3] << 8) | buf[2];
521 static int dm6444evm_mmc_get_cd(int module)
523 int status = dm6444evm_msp430_get_pins();
525 return (status < 0) ? status : !(status & BIT(1));
528 static int dm6444evm_mmc_get_ro(int module)
530 int status = dm6444evm_msp430_get_pins();
532 return (status < 0) ? status : status & BIT(6 + 8);
535 static struct davinci_mmc_config dm6446evm_mmc_config = {
536 .get_cd = dm6444evm_mmc_get_cd,
537 .get_ro = dm6444evm_mmc_get_ro,
539 .version = MMC_CTLR_VERSION_1
542 static struct i2c_board_info __initdata i2c_info[] = {
544 I2C_BOARD_INFO("dm6446evm_msp", 0x23),
547 I2C_BOARD_INFO("pcf8574", 0x38),
548 .platform_data = &pcf_data_u2,
551 I2C_BOARD_INFO("pcf8574", 0x39),
552 .platform_data = &pcf_data_u18,
555 I2C_BOARD_INFO("pcf8574", 0x3a),
556 .platform_data = &pcf_data_u35,
559 I2C_BOARD_INFO("24c256", 0x50),
560 .platform_data = &eeprom_info,
563 I2C_BOARD_INFO("tlv320aic33", 0x1b),
566 * - tvp5146 video decoder (0x5d)
570 /* The msp430 uses a slow bitbanged I2C implementation (ergo 20 KHz),
571 * which requires 100 usec of idle bus after i2c writes sent to it.
573 static struct davinci_i2c_platform_data i2c_pdata = {
574 .bus_freq = 20 /* kHz */,
575 .bus_delay = 100 /* usec */,
578 static void __init evm_init_i2c(void)
580 davinci_init_i2c(&i2c_pdata);
581 i2c_add_driver(&dm6446evm_msp_driver);
582 i2c_register_board_info(1, i2c_info, ARRAY_SIZE(i2c_info));
585 static struct platform_device *davinci_evm_devices[] __initdata = {
590 static struct davinci_uart_config uart_config __initdata = {
591 .enabled_uarts = (1 << 0),
595 davinci_evm_map_io(void)
600 static int davinci_phy_fixup(struct phy_device *phydev)
602 unsigned int control;
603 /* CRITICAL: Fix for increasing PHY signal drive strength for
604 * TX lockup issue. On DaVinci EVM, the Intel LXT971 PHY
605 * signal strength was low causing TX to fail randomly. The
606 * fix is to Set bit 11 (Increased MII drive strength) of PHY
607 * register 26 (Digital Config register) on this phy. */
608 control = phy_read(phydev, 26);
609 phy_write(phydev, 26, (control | 0x800));
613 #if defined(CONFIG_BLK_DEV_PALMCHIP_BK3710) || \
614 defined(CONFIG_BLK_DEV_PALMCHIP_BK3710_MODULE)
620 #if defined(CONFIG_MTD_PHYSMAP) || \
621 defined(CONFIG_MTD_PHYSMAP_MODULE)
627 #if defined(CONFIG_MTD_NAND_DAVINCI) || \
628 defined(CONFIG_MTD_NAND_DAVINCI_MODULE)
634 static __init void davinci_evm_init(void)
636 struct clk *aemif_clk;
637 struct davinci_soc_info *soc_info = &davinci_soc_info;
639 aemif_clk = clk_get(NULL, "aemif");
640 clk_enable(aemif_clk);
643 if (HAS_NAND || HAS_NOR)
644 pr_warning("WARNING: both IDE and Flash are "
645 "enabled, but they share AEMIF pins.\n"
646 "\tDisable IDE for NAND/NOR support.\n");
647 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
648 davinci_cfg_reg(DM644X_ATAEN);
649 davinci_cfg_reg(DM644X_HDIREN);
650 platform_device_register(&ide_dev);
651 } else if (HAS_NAND || HAS_NOR) {
652 davinci_cfg_reg(DM644X_HPIEN_DISABLE);
653 davinci_cfg_reg(DM644X_ATAEN_DISABLE);
655 /* only one device will be jumpered and detected */
657 platform_device_register(&davinci_evm_nandflash_device);
658 evm_leds[7].default_trigger = "nand-disk";
660 pr_warning("WARNING: both NAND and NOR flash "
661 "are enabled; disable one of them.\n");
663 platform_device_register(&davinci_evm_norflash_device);
666 platform_add_devices(davinci_evm_devices,
667 ARRAY_SIZE(davinci_evm_devices));
670 davinci_setup_mmc(0, &dm6446evm_mmc_config);
672 davinci_serial_init(&uart_config);
673 dm644x_init_asp(&dm644x_evm_snd_data);
675 soc_info->emac_pdata->phy_mask = DM644X_EVM_PHY_MASK;
676 soc_info->emac_pdata->mdio_max_freq = DM644X_EVM_MDIO_FREQUENCY;
678 /* Register the fixup for PHY on DaVinci */
679 phy_register_fixup_for_uid(LXT971_PHY_ID, LXT971_PHY_MASK,
684 static __init void davinci_evm_irq_init(void)
689 MACHINE_START(DAVINCI_EVM, "DaVinci DM644x EVM")
690 /* Maintainer: MontaVista Software <source@mvista.com> */
692 .io_pg_offst = (__IO_ADDRESS(IO_PHYS) >> 18) & 0xfffc,
693 .boot_params = (DAVINCI_DDR_BASE + 0x100),
694 .map_io = davinci_evm_map_io,
695 .init_irq = davinci_evm_irq_init,
696 .timer = &davinci_timer,
697 .init_machine = davinci_evm_init,