2 * derived from linux/arch/arm/mach-versatile/core.c
3 * linux/arch/arm/mach-bcmring/core.c
5 * Copyright (C) 1999 - 2003 ARM Limited
6 * Copyright (C) 2000 Deep Blue Solutions Ltd
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 /* Portions copyright Broadcom 2008 */
24 #include <linux/init.h>
25 #include <linux/device.h>
26 #include <linux/dma-mapping.h>
27 #include <linux/platform_device.h>
28 #include <linux/sysdev.h>
29 #include <linux/interrupt.h>
30 #include <linux/amba/bus.h>
31 #include <linux/clocksource.h>
32 #include <linux/clockchips.h>
34 #include <mach/csp/mm_addr.h>
35 #include <mach/hardware.h>
36 #include <asm/clkdev.h>
39 #include <asm/hardware/arm_timer.h>
40 #include <asm/mach-types.h>
42 #include <asm/mach/arch.h>
43 #include <asm/mach/flash.h>
44 #include <asm/mach/irq.h>
45 #include <asm/mach/time.h>
46 #include <asm/mach/map.h>
47 #include <asm/mach/mmc.h>
49 #include <cfg_global.h>
53 #include <csp/secHw.h>
54 #include <mach/csp/secHw_def.h>
55 #include <mach/csp/chipcHw_inline.h>
56 #include <mach/csp/tmrHw_reg.h>
58 #define AMBA_DEVICE(name, initname, base, plat, size) \
59 static struct amba_device name##_device = { \
61 .coherent_dma_mask = ~0, \
62 .init_name = initname, \
63 .platform_data = plat \
66 .start = MM_ADDR_IO_##base, \
67 .end = MM_ADDR_IO_##base + (size) - 1, \
68 .flags = IORESOURCE_MEM \
77 AMBA_DEVICE(uartA, "uarta", UARTA, NULL, SZ_4K);
78 AMBA_DEVICE(uartB, "uartb", UARTB, NULL, SZ_4K);
80 static struct clk pll1_clk = {
82 .type = CLK_TYPE_PRIMARY | CLK_TYPE_PLL1,
83 .rate_hz = 2000000000,
87 static struct clk uart_clk = {
89 .type = CLK_TYPE_PROGRAMMABLE,
90 .csp_id = chipcHw_CLOCK_UART,
91 .rate_hz = HW_CFG_UART_CLK_HZ,
95 static struct clk_lookup lookups[] = {
105 static struct amba_device *amba_devs[] __initdata = {
110 void __init bcmring_amba_init(void)
115 /* Linux is run initially in non-secure mode. Secure peripherals */
116 /* generate FIQ, and must be handled in secure mode. Until we have */
117 /* a linux security monitor implementation, keep everything in */
118 /* non-secure mode. */
119 chipcHw_busInterfaceClockEnable(chipcHw_REG_BUS_CLOCK_SPU);
120 secHw_setUnsecure(secHw_BLK_MASK_CHIP_CONTROL |
121 secHw_BLK_MASK_KEY_SCAN |
122 secHw_BLK_MASK_TOUCH_SCREEN |
123 secHw_BLK_MASK_UART0 |
124 secHw_BLK_MASK_UART1 |
125 secHw_BLK_MASK_WATCHDOG |
126 secHw_BLK_MASK_SPUM |
127 secHw_BLK_MASK_DDR2 |
133 secHw_BLK_MASK_BOOT |
135 secHw_BLK_MASK_TZCTRL | secHw_BLK_MASK_INTR);
137 /* Only the devices attached to the AMBA bus are enabled just before the bus is */
138 /* scanned and the drivers are loaded. The clocks need to be on for the AMBA bus */
139 /* driver to access these blocks. The bus is probed, and the drivers are loaded. */
140 /* FIXME Need to remove enable of PIF once CLCD clock enable used properly in FPGA. */
141 bus_clock = chipcHw_REG_BUS_CLOCK_GE
142 | chipcHw_REG_BUS_CLOCK_SDIO0 | chipcHw_REG_BUS_CLOCK_SDIO1;
144 chipcHw_busInterfaceClockEnable(bus_clock);
146 for (i = 0; i < ARRAY_SIZE(lookups); i++)
147 clkdev_add(&lookups[i]);
149 for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
150 struct amba_device *d = amba_devs[i];
151 amba_device_register(d, &iomem_resource);
156 * Where is the timer (VA)?
158 #define TIMER0_VA_BASE MM_IO_BASE_TMR
159 #define TIMER1_VA_BASE (MM_IO_BASE_TMR + 0x20)
160 #define TIMER2_VA_BASE (MM_IO_BASE_TMR + 0x40)
161 #define TIMER3_VA_BASE (MM_IO_BASE_TMR + 0x60)
163 /* Timer 0 - 25 MHz, Timer3 at bus clock rate, typically 150-166 MHz */
164 #if defined(CONFIG_ARCH_FPGA11107)
165 /* fpga cpu/bus are currently 30 times slower so scale frequency as well to */
166 /* slow down Linux's sense of time */
167 #define TIMER0_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
168 #define TIMER1_FREQUENCY_MHZ (tmrHw_LOW_FREQUENCY_MHZ * 30)
169 #define TIMER3_FREQUENCY_MHZ (tmrHw_HIGH_FREQUENCY_MHZ * 30)
170 #define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000 * 30)
172 #define TIMER0_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
173 #define TIMER1_FREQUENCY_MHZ tmrHw_LOW_FREQUENCY_MHZ
174 #define TIMER3_FREQUENCY_MHZ tmrHw_HIGH_FREQUENCY_MHZ
175 #define TIMER3_FREQUENCY_KHZ (tmrHw_HIGH_FREQUENCY_HZ / 1000)
178 #define TICKS_PER_uSEC TIMER0_FREQUENCY_MHZ
181 * These are useconds NOT ticks.
185 #define mSEC_5 (mSEC_1 * 5)
186 #define mSEC_10 (mSEC_1 * 10)
187 #define mSEC_25 (mSEC_1 * 25)
188 #define SEC_1 (mSEC_1 * 1000)
191 * How long is the timer interval?
193 #define TIMER_INTERVAL (TICKS_PER_uSEC * mSEC_10)
194 #if TIMER_INTERVAL >= 0x100000
195 #define TIMER_RELOAD (TIMER_INTERVAL >> 8)
196 #define TIMER_DIVISOR (TIMER_CTRL_DIV256)
197 #define TICKS2USECS(x) (256 * (x) / TICKS_PER_uSEC)
198 #elif TIMER_INTERVAL >= 0x10000
199 #define TIMER_RELOAD (TIMER_INTERVAL >> 4) /* Divide by 16 */
200 #define TIMER_DIVISOR (TIMER_CTRL_DIV16)
201 #define TICKS2USECS(x) (16 * (x) / TICKS_PER_uSEC)
203 #define TIMER_RELOAD (TIMER_INTERVAL)
204 #define TIMER_DIVISOR (TIMER_CTRL_DIV1)
205 #define TICKS2USECS(x) ((x) / TICKS_PER_uSEC)
208 static void timer_set_mode(enum clock_event_mode mode,
209 struct clock_event_device *clk)
214 case CLOCK_EVT_MODE_PERIODIC:
215 writel(TIMER_RELOAD, TIMER0_VA_BASE + TIMER_LOAD);
217 ctrl = TIMER_CTRL_PERIODIC;
219 TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE |
222 case CLOCK_EVT_MODE_ONESHOT:
223 /* period set, and timer enabled in 'next_event' hook */
224 ctrl = TIMER_CTRL_ONESHOT;
225 ctrl |= TIMER_DIVISOR | TIMER_CTRL_32BIT | TIMER_CTRL_IE;
227 case CLOCK_EVT_MODE_UNUSED:
228 case CLOCK_EVT_MODE_SHUTDOWN:
233 writel(ctrl, TIMER0_VA_BASE + TIMER_CTRL);
236 static int timer_set_next_event(unsigned long evt,
237 struct clock_event_device *unused)
239 unsigned long ctrl = readl(TIMER0_VA_BASE + TIMER_CTRL);
241 writel(evt, TIMER0_VA_BASE + TIMER_LOAD);
242 writel(ctrl | TIMER_CTRL_ENABLE, TIMER0_VA_BASE + TIMER_CTRL);
247 static struct clock_event_device timer0_clockevent = {
250 .features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
251 .set_mode = timer_set_mode,
252 .set_next_event = timer_set_next_event,
256 * IRQ handler for the timer
258 static irqreturn_t bcmring_timer_interrupt(int irq, void *dev_id)
260 struct clock_event_device *evt = &timer0_clockevent;
262 writel(1, TIMER0_VA_BASE + TIMER_INTCLR);
264 evt->event_handler(evt);
269 static struct irqaction bcmring_timer_irq = {
270 .name = "bcmring Timer Tick",
271 .flags = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
272 .handler = bcmring_timer_interrupt,
275 static cycle_t bcmring_get_cycles_timer1(void)
277 return ~readl(TIMER1_VA_BASE + TIMER_VALUE);
280 static cycle_t bcmring_get_cycles_timer3(void)
282 return ~readl(TIMER3_VA_BASE + TIMER_VALUE);
285 static struct clocksource clocksource_bcmring_timer1 = {
288 .read = bcmring_get_cycles_timer1,
289 .mask = CLOCKSOURCE_MASK(32),
291 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
294 static struct clocksource clocksource_bcmring_timer3 = {
297 .read = bcmring_get_cycles_timer3,
298 .mask = CLOCKSOURCE_MASK(32),
300 .flags = CLOCK_SOURCE_IS_CONTINUOUS,
303 static int __init bcmring_clocksource_init(void)
305 /* setup timer1 as free-running clocksource */
306 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
307 writel(0xffffffff, TIMER1_VA_BASE + TIMER_LOAD);
308 writel(0xffffffff, TIMER1_VA_BASE + TIMER_VALUE);
309 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
310 TIMER1_VA_BASE + TIMER_CTRL);
312 clocksource_bcmring_timer1.mult =
313 clocksource_khz2mult(TIMER1_FREQUENCY_MHZ * 1000,
314 clocksource_bcmring_timer1.shift);
315 clocksource_register(&clocksource_bcmring_timer1);
317 /* setup timer3 as free-running clocksource */
318 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
319 writel(0xffffffff, TIMER3_VA_BASE + TIMER_LOAD);
320 writel(0xffffffff, TIMER3_VA_BASE + TIMER_VALUE);
321 writel(TIMER_CTRL_32BIT | TIMER_CTRL_ENABLE | TIMER_CTRL_PERIODIC,
322 TIMER3_VA_BASE + TIMER_CTRL);
324 clocksource_bcmring_timer3.mult =
325 clocksource_khz2mult(TIMER3_FREQUENCY_KHZ,
326 clocksource_bcmring_timer3.shift);
327 clocksource_register(&clocksource_bcmring_timer3);
333 * Set up timer interrupt, and return the current time in seconds.
335 void __init bcmring_init_timer(void)
337 printk(KERN_INFO "bcmring_init_timer\n");
339 * Initialise to a known state (all timers off)
341 writel(0, TIMER0_VA_BASE + TIMER_CTRL);
342 writel(0, TIMER1_VA_BASE + TIMER_CTRL);
343 writel(0, TIMER2_VA_BASE + TIMER_CTRL);
344 writel(0, TIMER3_VA_BASE + TIMER_CTRL);
347 * Make irqs happen for the system timer
349 setup_irq(IRQ_TIMER0, &bcmring_timer_irq);
351 bcmring_clocksource_init();
353 timer0_clockevent.mult =
354 div_sc(1000000, NSEC_PER_SEC, timer0_clockevent.shift);
355 timer0_clockevent.max_delta_ns =
356 clockevent_delta2ns(0xffffffff, &timer0_clockevent);
357 timer0_clockevent.min_delta_ns =
358 clockevent_delta2ns(0xf, &timer0_clockevent);
360 timer0_clockevent.cpumask = cpumask_of(0);
361 clockevents_register_device(&timer0_clockevent);
364 struct sys_timer bcmring_timer = {
365 .init = bcmring_init_timer,