2 * arch/arm/include/asm/ptrace.h
4 * Copyright (C) 1996-2003 Russell King
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 #ifndef __ASM_ARM_PTRACE_H
11 #define __ASM_ARM_PTRACE_H
13 #include <asm/hwcap.h>
15 #define PTRACE_GETREGS 12
16 #define PTRACE_SETREGS 13
17 #define PTRACE_GETFPREGS 14
18 #define PTRACE_SETFPREGS 15
19 /* PTRACE_ATTACH is 16 */
20 /* PTRACE_DETACH is 17 */
21 #define PTRACE_GETWMMXREGS 18
22 #define PTRACE_SETWMMXREGS 19
24 #define PTRACE_OLDSETOPTIONS 21
25 #define PTRACE_GET_THREAD_AREA 22
26 #define PTRACE_SET_SYSCALL 23
27 /* PTRACE_SYSCALL is 24 */
28 #define PTRACE_GETCRUNCHREGS 25
29 #define PTRACE_SETCRUNCHREGS 26
30 #define PTRACE_GETVFPREGS 27
31 #define PTRACE_SETVFPREGS 28
36 #define USR26_MODE 0x00000000
37 #define FIQ26_MODE 0x00000001
38 #define IRQ26_MODE 0x00000002
39 #define SVC26_MODE 0x00000003
40 #define USR_MODE 0x00000010
41 #define FIQ_MODE 0x00000011
42 #define IRQ_MODE 0x00000012
43 #define SVC_MODE 0x00000013
44 #define ABT_MODE 0x00000017
45 #define UND_MODE 0x0000001b
46 #define SYSTEM_MODE 0x0000001f
47 #define MODE32_BIT 0x00000010
48 #define MODE_MASK 0x0000001f
49 #define PSR_T_BIT 0x00000020
50 #define PSR_F_BIT 0x00000040
51 #define PSR_I_BIT 0x00000080
52 #define PSR_A_BIT 0x00000100
53 #define PSR_J_BIT 0x01000000
54 #define PSR_Q_BIT 0x08000000
55 #define PSR_V_BIT 0x10000000
56 #define PSR_C_BIT 0x20000000
57 #define PSR_Z_BIT 0x40000000
58 #define PSR_N_BIT 0x80000000
63 #define PSR_f 0xff000000 /* Flags */
64 #define PSR_s 0x00ff0000 /* Status */
65 #define PSR_x 0x0000ff00 /* Extension */
66 #define PSR_c 0x000000ff /* Control */
69 * ARMv7 groups of APSR bits
71 #define PSR_ISET_MASK 0x01000010 /* ISA state (J, T) mask */
72 #define PSR_IT_MASK 0x0600fc00 /* If-Then execution state mask */
73 #define PSR_ENDIAN_MASK 0x00000200 /* Endianness state mask */
78 * This struct defines the way the registers are stored on the
79 * stack during a system call. Note that sizeof(struct pt_regs)
80 * has to be a multiple of 8.
86 #define ARM_cpsr uregs[16]
87 #define ARM_pc uregs[15]
88 #define ARM_lr uregs[14]
89 #define ARM_sp uregs[13]
90 #define ARM_ip uregs[12]
91 #define ARM_fp uregs[11]
92 #define ARM_r10 uregs[10]
93 #define ARM_r9 uregs[9]
94 #define ARM_r8 uregs[8]
95 #define ARM_r7 uregs[7]
96 #define ARM_r6 uregs[6]
97 #define ARM_r5 uregs[5]
98 #define ARM_r4 uregs[4]
99 #define ARM_r3 uregs[3]
100 #define ARM_r2 uregs[2]
101 #define ARM_r1 uregs[1]
102 #define ARM_r0 uregs[0]
103 #define ARM_ORIG_r0 uregs[17]
107 #define user_mode(regs) \
108 (((regs)->ARM_cpsr & 0xf) == 0)
110 #ifdef CONFIG_ARM_THUMB
111 #define thumb_mode(regs) \
112 (((regs)->ARM_cpsr & PSR_T_BIT))
114 #define thumb_mode(regs) (0)
117 #define isa_mode(regs) \
118 ((((regs)->ARM_cpsr & PSR_J_BIT) >> 23) | \
119 (((regs)->ARM_cpsr & PSR_T_BIT) >> 5))
121 #define processor_mode(regs) \
122 ((regs)->ARM_cpsr & MODE_MASK)
124 #define interrupts_enabled(regs) \
125 (!((regs)->ARM_cpsr & PSR_I_BIT))
127 #define fast_interrupts_enabled(regs) \
128 (!((regs)->ARM_cpsr & PSR_F_BIT))
130 /* Are the current registers suitable for user mode?
131 * (used to maintain security in signal handlers)
133 static inline int valid_user_regs(struct pt_regs *regs)
135 if (user_mode(regs) && (regs->ARM_cpsr & PSR_I_BIT) == 0) {
136 regs->ARM_cpsr &= ~(PSR_F_BIT | PSR_A_BIT);
141 * Force CPSR to something logical...
143 regs->ARM_cpsr &= PSR_f | PSR_s | (PSR_x & ~PSR_A_BIT) | PSR_T_BIT | MODE32_BIT;
144 if (!(elf_hwcap & HWCAP_26BIT))
145 regs->ARM_cpsr |= USR_MODE;
150 #define instruction_pointer(regs) (regs)->ARM_pc
153 extern unsigned long profile_pc(struct pt_regs *regs);
155 #define profile_pc(regs) instruction_pointer(regs)
158 #define predicate(x) ((x) & 0xf0000000)
159 #define PREDICATE_ALWAYS 0xe0000000
161 #endif /* __KERNEL__ */
163 #endif /* __ASSEMBLY__ */